aae7d4d5c8
BIOS_ERR is inappropriate since the init message is informational. Use BIOS_INFO instead. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I6fc15291a6d177a1b9e258d08e165224e5e10b32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67733 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
71 lines
1.9 KiB
C
71 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <ec/ec.h>
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#include <ec/google/chromeec/ec.h>
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#include <intelblocks/lpc_lib.h>
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#include <variant/ec.h>
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static void ramstage_ec_init(void)
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{
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const struct google_chromeec_event_info info = {
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.log_events = MAINBOARD_EC_LOG_EVENTS,
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.sci_events = MAINBOARD_EC_SCI_EVENTS,
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.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
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.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
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.s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
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};
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printk(BIOS_INFO, "mainboard: EC init\n");
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google_chromeec_events_init(&info, acpi_is_wakeup_s3());
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}
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static void bootblock_ec_init(void)
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{
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uint16_t ec_ioport_base;
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size_t ec_ioport_size;
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/*
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* Set up LPC decoding for the ChromeEC I/O port ranges:
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* - Ports 62/66, 60/64, and 200->208
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* - ChromeEC specific communication I/O ports.
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*/
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lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64
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| LPC_IOE_LGE_200);
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google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
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lpc_open_pmio_window(ec_ioport_base, ec_ioport_size);
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}
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void mainboard_ec_init(void)
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{
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if (CONFIG(EC_GOOGLE_CHROMEEC)) {
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if (ENV_RAMSTAGE)
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ramstage_ec_init();
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else if (ENV_BOOTBLOCK)
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bootblock_ec_init();
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} else if (ENV_BOOTBLOCK) {
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/*
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* Set up LPC decoding for the ChromeEC I/O port ranges:
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* - Ports 62/66, 60/64, and 200->208
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* - ChromeEC specific communication I/O ports.
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*/
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lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64
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| LPC_IOE_LGE_200);
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}
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if (CONFIG(GLK_INTEL_EC)) {
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printk(BIOS_ERR, "S3 Hack Enable ACPI mode: outb(0xaa,0x66)\n");
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outb(0xaa, 0x66);
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printk(BIOS_INFO, "Hack to turn on the CPU fan\n");
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outb(0x81, 0x66);
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outb(0x44, 0x62);
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outb(0x32, 0x62);
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/* Need delay here, hence second outb */
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outb(0x32, 0x62);
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outb(0x1a, 0x66);
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}
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}
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