ab1f217161
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
279 lines
6.4 KiB
C
279 lines
6.4 KiB
C
#define ASSEMBLY 1
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#define MAXIMUM_CONSOLE_LOGLEVEL 9
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#define DEFAULT_CONSOLE_LOGLEVEL 9
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <cpu/p6/apic.h>
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#include <arch/io.h>
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#include <device/pnp.h>
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#include <arch/romcc_io.h>
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
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#include "northbridge/amd/amdk8/raminit.h"
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#include "cpu/k8/apic_timer.c"
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#include "lib/delay.c"
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#include "cpu/p6/boot_cpu.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "debug.c"
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#define SIO_BASE 0x2e
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static void memreset_setup(void)
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{
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/* Set the memreset low */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
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/* Ensure the BIOS has control of the memory lines */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 30);
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 31);
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}
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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udelay(800);
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/* Set memreset_high */
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
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udelay(90);
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}
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/*
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* generate_row is specific to board implementation
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*
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*/
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static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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{
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/* Routing Table Node i
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*
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* F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
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* i: 0, 1, 2, 3, 4, 5, 6, 7
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*
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* [ 0: 3] Request Route
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* [0] Route to this node
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* [1] Route to Link 0
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* [2] Route to Link 1
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* [3] Route to Link 2
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* [11: 8] Response Route
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* [0] Route to this node
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* [1] Route to Link 0
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* [2] Route to Link 1
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* [3] Route to Link 2
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* [19:16] Broadcast route
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* [0] Route to this node
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* [1] Route to Link 0
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* [2] Route to Link 1
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* [3] Route to Link 2
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*/
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uint32_t ret=0x00010101; /* default row entry */
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static const unsigned int rows_2p[2][2] = {
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{ 0x00030101, 0x00010202 },
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{ 0x00010202, 0x00030101 }
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};
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static const unsigned int rows_4p[4][4] = {
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{ 0x00070101, 0x00010202, 0x00030404, 0x00010204 },
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{ 0x00010202, 0x000b0101, 0x00010208, 0x00030808 },
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{ 0x00030808, 0x00010208, 0x000b0101, 0x00010202 },
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{ 0x00010204, 0x00030404, 0x00010202, 0x00070101 }
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};
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if (!(node>=maxnodes || row>=maxnodes)) {
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if (maxnodes==2)
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ret=rows_2p[node][row];
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if (maxnodes==4)
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ret=rows_4p[node][row];
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}
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return ret;
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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#define SMBUS_HUB 0x30
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unsigned hub = device >> 8;
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device &= 0xff;
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// smbus_write_byte(SMBUS_HUB, hub);
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return smbus_read_byte(device, address);
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}
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/* no specific code here. this should go away completely */
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static void coherent_ht_mainboard(unsigned cpus)
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{
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}
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#include "northbridge/amd/amdk8/cpu_ldtstop.c"
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#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
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#include "northbridge/amd/amdk8/raminit.c"
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#define CONNECTION_0_1 UP
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#define CONNECTION_0_2 ACROSS
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#define CONNECTION_1_3 DOWN
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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#include "resourcemap.c" /* quartet does not want the default */
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static void enable_lapic(void)
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{
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msr_t msr;
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msr = rdmsr(0x1b);
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msr.hi &= 0xffffff00;
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msr.lo &= 0x000007ff;
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msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
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wrmsr(0x1b, msr);
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}
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static void stop_this_cpu(void)
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{
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unsigned apicid;
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apicid = apic_read(APIC_ID) >> 24;
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/* Send an APIC INIT to myself */
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apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
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/* Wait for the ipi send to finish */
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apic_wait_icr_idle();
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/* Deassert the APIC INIT */
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apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
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/* Wait for the ipi send to finish */
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apic_wait_icr_idle();
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/* If I haven't halted spin forever */
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for(;;) {
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hlt();
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}
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}
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#define PC87360_FDC 0x00
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#define PC87360_PP 0x01
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#define PC87360_SP2 0x02
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#define PC87360_SP1 0x03
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#define PC87360_SWC 0x04
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#define PC87360_KBCM 0x05
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#define PC87360_KBCK 0x06
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#define PC87360_GPIO 0x07
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#define PC87360_ACB 0x08
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#define PC87360_FSCM 0x09
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#define PC87360_WDT 0x0A
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static void pc87360_enable_serial(void)
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{
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pnp_set_logical_device(SIO_BASE, PC87360_SP1);
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pnp_set_enable(SIO_BASE, 1);
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pnp_set_iobase0(SIO_BASE, 0x3f8);
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}
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#define RC0 (0<<8)
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#define RC1 (1<<8)
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#define RC2 (2<<8)
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#define RC3 (3<<8)
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#define DIMM0 0xa0
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#define DIMM1 0xa2
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#define DIMM2 0xa4
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#define DIMM3 0xa8
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static void main(void)
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{
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static const struct mem_controller cpu[] = {
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{
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.node_id = 0,
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.f0 = PCI_DEV(0, 0x18, 0),
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.f1 = PCI_DEV(0, 0x18, 1),
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.f2 = PCI_DEV(0, 0x18, 2),
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.f3 = PCI_DEV(0, 0x18, 3),
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.channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
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.channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
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},
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{
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.node_id = 1,
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.f0 = PCI_DEV(0, 0x19, 0),
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.f1 = PCI_DEV(0, 0x19, 1),
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.f2 = PCI_DEV(0, 0x19, 2),
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.f3 = PCI_DEV(0, 0x19, 3),
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.channel0 = { RC1|DIMM0, RC1|DIMM2, 0, 0 },
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.channel1 = { RC1|DIMM1, RC1|DIMM3, 0, 0 },
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},
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{
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.node_id = 2,
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.f0 = PCI_DEV(0, 0x1a, 0),
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.f1 = PCI_DEV(0, 0x1a, 1),
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.f2 = PCI_DEV(0, 0x1a, 2),
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.f3 = PCI_DEV(0, 0x1a, 3),
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.channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
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.channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
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},
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{
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.node_id = 3,
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.f0 = PCI_DEV(0, 0x1b, 0),
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.f1 = PCI_DEV(0, 0x1b, 1),
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.f2 = PCI_DEV(0, 0x1b, 2),
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.f3 = PCI_DEV(0, 0x1b, 3),
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.channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
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.channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
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}
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};
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if (cpu_init_detected()) {
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asm("jmp __cpu_reset");
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}
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enable_lapic();
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init_timer();
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if (!boot_cpu()) {
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// notify_bsp_ap_is_stopped();
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stop_this_cpu();
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}
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pc87360_enable_serial();
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uart_init();
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console_init();
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setup_quartet_resource_map();
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setup_coherent_ht_domain();
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enumerate_ht_chain(0);
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distinguish_cpu_resets(0);
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#if 0
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print_pci_devices();
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#endif
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enable_smbus();
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#if 0
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dump_spd_registers(&cpu[0]);
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#endif
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memreset_setup();
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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#if 0
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dump_pci_devices();
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#endif
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#if 0
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dump_pci_device(PCI_DEV(0, 0x18, 2));
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#endif
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/* Check all of memory */
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#if 0
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msr_t msr;
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msr = rdmsr(TOP_MEM);
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print_debug("TOP_MEM: ");
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print_debug_hex32(msr.hi);
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print_debug_hex32(msr.lo);
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print_debug("\r\n");
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#endif
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#if 0
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ram_check(0x00000000, msr.lo);
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#else
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/* Check 16MB of memory */
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ram_check(0x00000000, 0x01000000);
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#endif
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}
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