ab368d96d7
By ACPI specification, those follow GPE0_EN bits in the register space. Use sizeof() to replace the 2/4 offset previously used. Change-Id: I27ada0b19b2cf5e8eca71f48bf103dcab1b3cc11 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
169 lines
3.9 KiB
C
169 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/io.h>
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#include <acpi/acpi.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <stdint.h>
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#include <elog.h>
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#include "pch.h"
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static void pch_log_standard_gpe(u32 gpe0_sts_reg, u32 gpe0_en_reg)
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{
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u32 gpe0_en = inl(get_pmbase() + gpe0_en_reg);
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u32 gpe0_sts = inl(get_pmbase() + gpe0_sts_reg) & gpe0_en;
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/* PME (TODO: determine wake device) */
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if (gpe0_sts & PME_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
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/* Internal PME (TODO: determine wake device) */
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if (gpe0_sts & PME_B0_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
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/* SMBUS Wake */
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if (gpe0_sts & SMB_WAK_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
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}
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static void pch_log_gpio_gpe(u32 gpe0_sts_reg, u32 gpe0_en_reg, int start)
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{
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/* GPE Bank 1 is GPIO 0-31 */
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u32 gpe0_en = inl(get_pmbase() + gpe0_en_reg);
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u32 gpe0_sts = inl(get_pmbase() + gpe0_sts_reg) & gpe0_en;
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int i;
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for (i = 0; i <= 31; i++) {
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if (gpe0_sts & (1 << i))
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elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start);
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}
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}
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static void pch_log_gpe(void)
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{
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int i;
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u16 pmbase = get_pmbase();
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u32 gpe0_sts, gpe0_en;
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int gpe0_high_gpios[] = {
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[0] = 27,
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[24] = 17,
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[25] = 19,
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[26] = 21,
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[27] = 22,
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[28] = 43,
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[29] = 56,
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[30] = 57,
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[31] = 60
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};
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pch_log_standard_gpe(GPE0_EN, GPE0_STS);
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/* GPIO 0-15 */
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gpe0_en = inw(pmbase + GPE0_EN + sizeof(uint16_t));
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gpe0_sts = inw(pmbase + GPE0_STS + sizeof(uint16_t)) & gpe0_en;
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for (i = 0; i <= 15; i++) {
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if (gpe0_sts & (1 << i))
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elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i);
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}
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/*
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* Now check and log upper status bits
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*/
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gpe0_en = inl(pmbase + GPE0_EN + sizeof(uint32_t));
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gpe0_sts = inl(pmbase + GPE0_STS + sizeof(uint32_t)) & gpe0_en;
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for (i = 0; i <= 31; i++) {
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if (!gpe0_high_gpios[i])
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continue;
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if (gpe0_sts & (1 << i))
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elog_add_event_wake(ELOG_WAKE_SOURCE_GPE,
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gpe0_high_gpios[i]);
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}
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}
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static void pch_lp_log_gpe(void)
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{
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/* Standard GPE are in GPE set 4 */
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pch_log_standard_gpe(LP_GPE0_STS_4, LP_GPE0_EN_4);
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/* Log GPIO events in set 1-3 */
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pch_log_gpio_gpe(LP_GPE0_STS_1, LP_GPE0_EN_1, 0);
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pch_log_gpio_gpe(LP_GPE0_STS_2, LP_GPE0_EN_2, 32);
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pch_log_gpio_gpe(LP_GPE0_STS_3, LP_GPE0_EN_3, 64);
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}
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void pch_log_state(void)
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{
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u16 pm1_sts, gen_pmcon_3, tco2_sts;
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u8 gen_pmcon_2;
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struct device *lpc = pcidev_on_root(0x1f, 0);
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if (!lpc)
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return;
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pm1_sts = inw(get_pmbase() + PM1_STS);
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tco2_sts = inw(get_pmbase() + TCO2_STS);
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gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2);
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gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3);
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/* PWR_FLR Power Failure */
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if (gen_pmcon_2 & PWROK_FLR)
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elog_add_event(ELOG_TYPE_POWER_FAIL);
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/* SUS Well Power Failure */
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if (gen_pmcon_3 & SUS_PWR_FLR)
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elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
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/* SYS_PWROK Failure */
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if (gen_pmcon_2 & SYSPWR_FLR)
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elog_add_event(ELOG_TYPE_SYS_PWROK_FAIL);
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/* PWROK Failure */
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if (gen_pmcon_2 & PWROK_FLR)
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elog_add_event(ELOG_TYPE_PWROK_FAIL);
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/* Second TCO Timeout */
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if (tco2_sts & TCO2_STS_SECOND_TO)
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elog_add_event(ELOG_TYPE_TCO_RESET);
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/* Power Button Override */
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if (pm1_sts & PRBTNOR_STS)
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elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
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/* System Reset Status (reset button pushed) */
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if (gen_pmcon_2 & SYSTEM_RESET_STS)
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elog_add_event(ELOG_TYPE_RESET_BUTTON);
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/* General Reset Status */
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if (gen_pmcon_3 & GEN_RST_STS)
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elog_add_event(ELOG_TYPE_SYSTEM_RESET);
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/* ACPI Wake */
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if (pm1_sts & WAK_STS)
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elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
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acpi_is_wakeup_s3() ? 3 : 5);
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/*
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* Wake sources
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*/
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/* Power Button */
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if (pm1_sts & PWRBTN_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
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/* RTC */
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if (pm1_sts & RTC_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
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/* PCI Express (TODO: determine wake device) */
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if (pm1_sts & PCIEXPWAK_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
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/* GPE */
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if (pch_is_lp())
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pch_lp_log_gpe();
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else
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pch_log_gpe();
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}
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