system76-coreboot

Files

Scott Chao ab58d2b488 mb/google/brya/var/crota: Limit dram speed to 4800 MT/s

When using LPDDR5 on a Type-C PCB, the Intel ADL-P PDG (Rev. 2.0.1)
page 121 recommends a maximum DRAM speed of 4800 MT/s.

BUG=b:229549930
BRANCH=none
TEST=build and pass memory training

Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I38f0006d478702afb382d30338f20b46641964ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

2022-04-27 12:27:25 +00:00

acpi

lib/hardwaremain.c: Move creating ACPI structs to bootstate hooks

2022-04-27 10:56:47 +00:00

arch

arch/x86/acpi_bert_storage.c: Use BOOT_STATE over CBMEM hooks

2022-04-25 16:34:44 +00:00

commonlib

commonlib: Replace 'stdlib' with 'stddef'

2022-04-24 18:31:14 +00:00

console

console: Make CONSOLE_SPI_FLASH depend on BOOT_DEVICE_SPI_FLASH