9de060fd34
This is already the case on x86 but not on the ARM platforms, and
{read,write}[bwl] are using volatile pointers, too, so follow suit.
Change-Id: I6819df62016990e12410eaa9c3c97b8b90944b51
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
136 lines
3.3 KiB
C
136 lines
3.3 KiB
C
/*
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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* Copyright (C) 2008 coresystems GmbH
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _ARCH_IO_H
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#define _ARCH_IO_H
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#include <stdint.h>
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#include <arch/cache.h>
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/*
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* readb/w/l writeb/w/l are deprecated. use read8/16/32 and write8/16/32
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* instead for future development.
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*
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* TODO: make the existing code use read8/16/32 and write8/16/32 then remove
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* readb/w/l and writeb/w/l.
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*/
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static inline uint8_t readb(volatile const void *_a)
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{
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dmb();
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return *(volatile const uint8_t *)_a;
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}
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static inline uint16_t readw(volatile const void *_a)
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{
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dmb();
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return *(volatile const uint16_t *)_a;
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}
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static inline uint32_t readl(volatile const void *_a)
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{
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dmb();
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return *(volatile const uint32_t *)_a;
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}
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static inline void writeb(uint8_t _v, volatile void *_a)
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{
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dmb();
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*(volatile uint8_t *)_a = _v;
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dmb();
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}
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static inline void writew(uint16_t _v, volatile void *_a)
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{
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dmb();
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*(volatile uint16_t *)_a = _v;
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dmb();
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}
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static inline void writel(uint32_t _v, volatile void *_a)
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{
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dmb();
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*(volatile uint32_t *)_a = _v;
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dmb();
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}
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static inline uint8_t read8(volatile const void *addr)
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{
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dmb();
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return *(volatile uint8_t *)addr;
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}
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static inline uint16_t read16(volatile const void *addr)
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{
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dmb();
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return *(volatile uint16_t *)addr;
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}
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static inline uint32_t read32(volatile const void *addr)
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{
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dmb();
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return *(volatile uint32_t *)addr;
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}
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static inline uint64_t read64(volatile const void *addr)
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{
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dmb();
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return *(volatile uint64_t *)addr;
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}
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static inline void write8(volatile void *addr, uint8_t val)
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{
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dmb();
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*(volatile uint8_t *)addr = val;
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dmb();
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}
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static inline void write16(volatile void *addr, uint16_t val)
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{
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dmb();
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*(volatile uint16_t *)addr = val;
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dmb();
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}
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static inline void write32(volatile void *addr, uint32_t val)
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{
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dmb();
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*(volatile uint32_t *)addr = val;
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dmb();
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}
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static inline void write64(volatile void *addr, uint64_t val)
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{
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dmb();
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*(volatile uint64_t *)addr = val;
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dmb();
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}
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#endif
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