ab89edbccf
<types.h> is supposed to provide <stdint.h> and <stddef.h>. When <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: I4d8628e4ce3c7f80da2590b4cad618b290e0d513 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
135 lines
3.3 KiB
C
135 lines
3.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <device/mmio.h>
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#include <arch/acpi.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <types.h>
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#include "hudson.h"
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#include "smbus.h"
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#include "smi.h"
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#include "fchec.h"
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int acpi_get_sleep_type(void)
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{
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u16 tmp = inw(ACPI_PM1_CNT_BLK);
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tmp = ((tmp & (7 << 10)) >> 10);
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return (int)tmp;
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}
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void pm_write8(u8 reg, u8 value)
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{
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write8((void *)(PM_MMIO_BASE + reg), value);
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}
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u8 pm_read8(u8 reg)
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{
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return read8((void *)(PM_MMIO_BASE + reg));
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}
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void pm_write16(u8 reg, u16 value)
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{
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write16((void *)(PM_MMIO_BASE + reg), value);
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}
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u16 pm_read16(u16 reg)
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{
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return read16((void *)(PM_MMIO_BASE + reg));
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}
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void hudson_enable(struct device *dev)
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{
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printk(BIOS_DEBUG, "hudson_enable()\n");
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switch (dev->path.pci.devfn) {
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case PCI_DEVFN(0x14, 7): /* SD */
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if (dev->enabled == 0) {
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u32 sd_device_id = pci_read_config16(dev, PCI_DEVICE_ID);
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/* turn off the SDHC controller in the PM reg */
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u8 reg8;
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if (sd_device_id == PCI_DEVICE_ID_AMD_HUDSON_SD) {
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reg8 = pm_read8(PM_HUD_SD_FLASH_CTRL);
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reg8 &= ~BIT(0);
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pm_write8(PM_HUD_SD_FLASH_CTRL, reg8);
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}
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else if (sd_device_id == PCI_DEVICE_ID_AMD_YANGTZE_SD) {
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reg8 = pm_read8(PM_YANG_SD_FLASH_CTRL);
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reg8 &= ~BIT(0);
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pm_write8(PM_YANG_SD_FLASH_CTRL, reg8);
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}
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/* remove device 0:14.7 from PCI space */
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reg8 = pm_read8(PM_MANUAL_RESET);
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reg8 &= ~BIT(6);
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pm_write8(PM_MANUAL_RESET, reg8);
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}
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break;
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default:
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break;
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}
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}
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static void hudson_init_acpi_ports(void)
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{
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/* We use some of these ports in SMM regardless of whether or not
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* ACPI tables are generated. Enable these ports indiscriminately.
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*/
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pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK);
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pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK);
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pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
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pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
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/* CpuControl is in \_PR.CP00, 6 bytes */
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pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL);
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if (CONFIG(HAVE_SMI_HANDLER)) {
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pm_write16(PM_ACPI_SMI_CMD, ACPI_SMI_CTL_PORT);
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hudson_enable_acpi_cmd_smi();
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} else {
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pm_write16(PM_ACPI_SMI_CMD, 0);
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}
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/* AcpiDecodeEnable, When set, SB uses the contents of the PM registers
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* at index 60-6B to decode ACPI I/O address. AcpiSmiEn & SmiCmdEn
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*/
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pm_write8(PM_ACPI_CONF, BIT(0) | BIT(1) | BIT(4) | BIT(2));
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}
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static void hudson_init(void *chip_info)
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{
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hudson_init_acpi_ports();
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}
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static void hudson_final(void *chip_info)
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{
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if (CONFIG(HUDSON_IMC_FWM)) {
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agesawrapper_fchecfancontrolservice();
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if (!CONFIG(ACPI_ENABLE_THERMAL_ZONE))
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enable_imc_thermal_zone();
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}
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}
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struct chip_operations southbridge_amd_pi_hudson_ops = {
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CHIP_NAME("ATI HUDSON")
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.enable_dev = hudson_enable,
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.init = hudson_init,
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.final = hudson_final
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};
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