accb50a4e3
does not work as it is, but it's the only compile test case for i855pm). It's the only board left using an ICH4 that does not use CAR. Change that. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
39 lines
816 B
Plaintext
39 lines
816 B
Plaintext
config BOARD_DIGITALLOGIC_ADL855PC
|
|
bool "smartModule855"
|
|
select ARCH_X86
|
|
select CPU_INTEL_SOCKET_MPGA479M
|
|
select NORTHBRIDGE_INTEL_I855
|
|
select SOUTHBRIDGE_INTEL_I82801DX
|
|
select SUPERIO_WINBOND_W83627HF
|
|
select HAVE_PIRQ_TABLE
|
|
select HAVE_HARD_RESET
|
|
select BOARD_ROMSIZE_KB_1024
|
|
select USE_PRINTK_IN_CAR
|
|
select USE_DCACHE_RAM
|
|
select TINY_BOOTBLOCK
|
|
|
|
config MAINBOARD_DIR
|
|
string
|
|
default digitallogic/adl855pc
|
|
depends on BOARD_DIGITALLOGIC_ADL855PC
|
|
|
|
config MAINBOARD_PART_NUMBER
|
|
string
|
|
default "smartModule855"
|
|
depends on BOARD_DIGITALLOGIC_ADL855PC
|
|
|
|
config DCACHE_RAM_BASE
|
|
hex
|
|
default 0xffdf8000
|
|
depends on BOARD_DIGITALLOGIC_ADL855PC
|
|
|
|
config DCACHE_RAM_SIZE
|
|
hex
|
|
default 0x8000
|
|
depends on BOARD_DIGITALLOGIC_ADL855PC
|
|
|
|
config IRQ_SLOT_COUNT
|
|
int
|
|
default 5
|
|
depends on BOARD_DIGITALLOGIC_ADL855PC
|