aced1f02cf
Derived from Broadwell and adapted to follow what soc/intel does. Note that SERIALIO_UART_CONSOLE is meant to be selected from the mainboards which expose a SerialIO UART. UART_FOR_CONSOLE also needs to be set in mainboard Kconfig accordingly. It is possible that some of the UART configuration steps in bootblock are unnecessary. However, some of the steps turn off power management features and others are undocumented: omitting them could cause weird issues. Finally, add a config file to ensure the code gets build-tested. Tested on out-of-tree Compal LA-A992P, SerialIO UART 0 can be used to receive coreboot and SeaBIOS logs. Change-Id: Ifb3460dd50ed03421a38f03c80f91ae9fd604022 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52489 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
278 lines
7.5 KiB
C
278 lines
7.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <acpi/acpi_gnvs.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <soc/nvs.h>
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#include <types.h>
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#include "chip.h"
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#include "iobp.h"
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#include "pch.h"
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/* Enable clock in PCI mode */
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static void serialio_enable_clock(struct resource *bar0)
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{
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u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0));
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reg32 |= SIO_REG_PPR_CLOCK_EN;
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write32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0), reg32);
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}
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static bool serialio_uart_is_debug(struct device *dev)
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{
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if (CONFIG(SERIALIO_UART_CONSOLE)) {
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switch (dev->path.pci.devfn) {
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case PCH_DEVFN_UART0:
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return CONFIG_UART_FOR_CONSOLE == 0;
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case PCH_DEVFN_UART1:
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return CONFIG_UART_FOR_CONSOLE == 1;
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}
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}
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return 0;
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}
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/* Put Serial IO D21:F0-F6 device into desired mode. */
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static void serialio_d21_mode(int sio_index, int int_pin, int acpi_mode)
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{
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u32 portctrl = SIO_IOBP_PORTCTRL_PM_CAP_PRSNT;
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/* Snoop select 1. */
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portctrl |= SIO_IOBP_PORTCTRL_SNOOP_SELECT(1);
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/* Set interrupt pin. */
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portctrl |= SIO_IOBP_PORTCTRL_INT_PIN(int_pin);
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if (acpi_mode) {
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/* Enable ACPI interrupt mode. */
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portctrl |= SIO_IOBP_PORTCTRL_ACPI_IRQ_EN;
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/* Disable PCI config space. */
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portctrl |= SIO_IOBP_PORTCTRL_PCI_CONF_DIS;
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}
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pch_iobp_update(SIO_IOBP_PORTCTRLX(sio_index), 0, portctrl);
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}
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/* Put Serial IO D23:F0 device into desired mode. */
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static void serialio_d23_mode(int acpi_mode)
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{
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u32 portctrl = 0;
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/* Snoop select 1. */
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pch_iobp_update(SIO_IOBP_PORTCTRL1, 0,
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SIO_IOBP_PORTCTRL1_SNOOP_SELECT(1));
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if (acpi_mode) {
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/* Enable ACPI interrupt mode. */
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portctrl |= SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN;
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/* Disable PCI config space. */
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portctrl |= SIO_IOBP_PORTCTRL0_PCI_CONF_DIS;
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}
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pch_iobp_update(SIO_IOBP_PORTCTRL0, 0, portctrl);
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}
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/* Enable LTR Auto Mode for D21:F1-F6. */
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static void serialio_d21_ltr(struct resource *bar0)
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{
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u32 reg;
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/* 1. Program BAR0 + 808h[2] = 0b */
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reg = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0));
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reg &= ~SIO_REG_PPR_GEN_LTR_MODE_MASK;
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write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg);
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/* 2. Program BAR0 + 804h[1:0] = 00b */
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reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0));
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reg &= ~SIO_REG_PPR_RST_ASSERT;
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write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg);
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/* 3. Program BAR0 + 804h[1:0] = 11b */
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reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0));
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reg |= SIO_REG_PPR_RST_ASSERT;
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write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg);
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/* 4. Program BAR0 + 814h[31:0] = 00000000h */
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write32(res2mmio(bar0, SIO_REG_AUTO_LTR, 0), 0);
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}
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/* Enable LTR Auto Mode for D23:F0. */
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static void serialio_d23_ltr(struct resource *bar0)
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{
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u32 reg;
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/* Program BAR0 + 1008h[2] = 1b */
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reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0));
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reg |= SIO_REG_PPR_GEN_LTR_MODE_MASK;
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write32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0), reg);
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/* Program BAR0 + 1010h = 0x00000000 */
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write32(res2mmio(bar0, SIO_REG_SDIO_PPR_SW_LTR, 0), 0);
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/* Program BAR0 + 3Ch[30] = 1b */
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reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0));
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reg |= SIO_REG_SDIO_PPR_CMD12_B30;
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write32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0), reg);
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}
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/* Select I2C voltage of 1.8V or 3.3V. */
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static void serialio_i2c_voltage_sel(struct resource *bar0, u8 voltage)
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{
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u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0));
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reg32 &= ~SIO_REG_PPR_GEN_VOLTAGE_MASK;
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reg32 |= SIO_REG_PPR_GEN_VOLTAGE(voltage);
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write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg32);
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}
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/* Init sequence to be run once, done as part of D21:F0 (SDMA) init. */
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static void serialio_init_once(int acpi_mode)
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{
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if (acpi_mode) {
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/* Enable ACPI IRQ for IRQ13, IRQ7, IRQ6, IRQ5 in RCBA. */
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RCBA32_OR(ACPIIRQEN, (1 << 13) | (1 << 7) | (1 << 6) | (1 << 5));
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}
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/* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b. */
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pch_iobp_update(SIO_IOBP_GPIODF, ~0x0000131f, 0x0000131f);
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/* Program IOBP CB000180h[5:0] = 111111b (undefined register) */
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pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f);
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}
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static void update_bars(int sio_index, u32 bar0, u32 bar1)
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{
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/* Find ACPI NVS to update BARs */
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struct global_nvs *gnvs = acpi_get_gnvs();
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if (!gnvs)
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return;
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gnvs->s0b[sio_index] = bar0;
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gnvs->s1b[sio_index] = bar1;
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}
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static void serialio_init(struct device *dev)
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{
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struct southbridge_intel_lynxpoint_config *config = config_of(dev);
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struct resource *bar0, *bar1;
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int sio_index = -1;
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printk(BIOS_DEBUG, "Initializing Serial IO device\n");
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/* Ensure memory and bus master are enabled */
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pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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/* Find BAR0 and BAR1 */
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bar0 = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (!bar0)
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return;
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bar1 = find_resource(dev, PCI_BASE_ADDRESS_1);
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if (!bar1)
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return;
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if (!config->sio_acpi_mode)
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serialio_enable_clock(bar0);
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switch (dev->path.pci.devfn) {
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case PCH_DEVFN_SDMA: /* SDMA */
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sio_index = SIO_ID_SDMA;
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serialio_init_once(config->sio_acpi_mode);
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serialio_d21_mode(sio_index, SIO_PIN_INTB,
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config->sio_acpi_mode);
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break;
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case PCH_DEVFN_I2C0: /* I2C0 */
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sio_index = SIO_ID_I2C0;
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serialio_d21_ltr(bar0);
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serialio_i2c_voltage_sel(bar0, config->sio_i2c0_voltage);
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serialio_d21_mode(sio_index, SIO_PIN_INTC,
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config->sio_acpi_mode);
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break;
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case PCH_DEVFN_I2C1: /* I2C1 */
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sio_index = SIO_ID_I2C1;
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serialio_d21_ltr(bar0);
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serialio_i2c_voltage_sel(bar0, config->sio_i2c1_voltage);
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serialio_d21_mode(sio_index, SIO_PIN_INTC,
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config->sio_acpi_mode);
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break;
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case PCH_DEVFN_SPI0: /* SPI0 */
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sio_index = SIO_ID_SPI0;
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serialio_d21_ltr(bar0);
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serialio_d21_mode(sio_index, SIO_PIN_INTC,
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config->sio_acpi_mode);
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break;
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case PCH_DEVFN_SPI1: /* SPI1 */
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sio_index = SIO_ID_SPI1;
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serialio_d21_ltr(bar0);
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serialio_d21_mode(sio_index, SIO_PIN_INTC,
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config->sio_acpi_mode);
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break;
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case PCH_DEVFN_UART0: /* UART0 */
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sio_index = SIO_ID_UART0;
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if (!serialio_uart_is_debug(dev))
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serialio_d21_ltr(bar0);
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serialio_d21_mode(sio_index, SIO_PIN_INTD,
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config->sio_acpi_mode);
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break;
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case PCH_DEVFN_UART1: /* UART1 */
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sio_index = SIO_ID_UART1;
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if (!serialio_uart_is_debug(dev))
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serialio_d21_ltr(bar0);
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serialio_d21_mode(sio_index, SIO_PIN_INTD,
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config->sio_acpi_mode);
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break;
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case PCH_DEVFN_SDIO: /* SDIO */
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sio_index = SIO_ID_SDIO;
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serialio_d23_ltr(bar0);
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serialio_d23_mode(config->sio_acpi_mode);
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break;
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default:
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return;
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}
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/* Save BAR0 and BAR1 to ACPI NVS */
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if (config->sio_acpi_mode)
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update_bars(sio_index, (u32)bar0->base, (u32)bar1->base);
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}
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static void serialio_read_resources(struct device *dev)
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{
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pci_dev_read_resources(dev);
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/* Set the configured UART base address for the debug port */
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if (CONFIG(SERIALIO_UART_CONSOLE) && serialio_uart_is_debug(dev)) {
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struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
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res->base = CONFIG_CONSOLE_UART_BASE_ADDRESS;
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res->size = 0x1000;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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}
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}
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static struct device_operations device_ops = {
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.read_resources = serialio_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = serialio_init,
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.ops_pci = &pci_dev_ops_pci,
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};
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static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_LPT_LP_SDMA,
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PCI_DEVICE_ID_INTEL_LPT_LP_I2C0,
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PCI_DEVICE_ID_INTEL_LPT_LP_I2C1,
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PCI_DEVICE_ID_INTEL_LPT_LP_GSPI0,
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PCI_DEVICE_ID_INTEL_LPT_LP_GSPI1,
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PCI_DEVICE_ID_INTEL_LPT_LP_UART0,
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PCI_DEVICE_ID_INTEL_LPT_LP_UART1,
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PCI_DEVICE_ID_INTEL_LPT_LP_SD,
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0
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};
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static const struct pci_driver pch_pcie __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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