aced1f02cf
Derived from Broadwell and adapted to follow what soc/intel does. Note that SERIALIO_UART_CONSOLE is meant to be selected from the mainboards which expose a SerialIO UART. UART_FOR_CONSOLE also needs to be set in mainboard Kconfig accordingly. It is possible that some of the UART configuration steps in bootblock are unnecessary. However, some of the steps turn off power management features and others are undocumented: omitting them could cause weird issues. Finally, add a config file to ensure the code gets build-tested. Tested on out-of-tree Compal LA-A992P, SerialIO UART 0 can be used to receive coreboot and SeaBIOS logs. Change-Id: Ifb3460dd50ed03421a38f03c80f91ae9fd604022 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52489 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
55 lines
1.6 KiB
C
55 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/io.h>
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#include <arch/mmio.h>
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#include <assert.h>
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#include <console/uart.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <southbridge/intel/lynxpoint/iobp.h>
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#include <southbridge/intel/lynxpoint/lp_gpio.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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#include <types.h>
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static pci_devfn_t get_uart_pci_device(void)
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{
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switch (CONFIG_UART_FOR_CONSOLE) {
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case 0: return PCI_DEV(0, 0x15, 5);
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case 1: return PCI_DEV(0, 0x15, 6);
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default: return dead_code_t(pci_devfn_t);
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}
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}
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/* TODO: Figure out if all steps are actually necessary */
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void uart_bootblock_init(void)
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{
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const pci_devfn_t dev = get_uart_pci_device();
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/* Program IOBP GPIODF */
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pch_iobp_update(SIO_IOBP_GPIODF, ~0x131f, 0x131f);
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/* Program IOBP CB000180h[5:0] = 111111b (undefined register) */
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pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f);
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/* Set and enable MMIO BAR */
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_CONSOLE_UART_BASE_ADDRESS);
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pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
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void *const bar = (void *)(uintptr_t)CONFIG_CONSOLE_UART_BASE_ADDRESS;
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/* Initialize LTR */
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clrbits32(bar + SIO_REG_PPR_GEN, SIO_REG_PPR_GEN_LTR_MODE_MASK);
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clrbits32(bar + SIO_REG_PPR_RST, SIO_REG_PPR_RST_ASSERT);
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/* Take UART out of reset */
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setbits32(bar + SIO_REG_PPR_RST, SIO_REG_PPR_RST_ASSERT);
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/* Set M and N divisor inputs and enable clock */
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uint32_t ppr_clock = 0;
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ppr_clock |= SIO_REG_PPR_CLOCK_EN;
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ppr_clock |= SIO_REG_PPR_CLOCK_UPDATE;
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ppr_clock |= SIO_REG_PPR_CLOCK_N_DIV << 16;
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ppr_clock |= SIO_REG_PPR_CLOCK_M_DIV << 1;
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write32(bar + SIO_REG_PPR_CLOCK, ppr_clock);
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}
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