ca52a25882
This patch adds the new, faster architectural register accessors to libpayload that were already added to coreboot in CB:27881. It also hardcodes the assumption that coreboot payloads run at EL2, which has already been hardcoded in coreboot with CB:27880 (see rationale there). This means we can drop all the read_current/write_current stuff which added a lot of unnecessary helpers to check the current exception level. This patch breaks payloads that used read_current/write_current accessors, but it seems unlikely that many payloads deal with this stuff anyway, and it should be a trivial fix (just replace them with the respective _el2 versions). Also add accessors for a couple of more registers that are required to enable debug mode while I'm here. Change-Id: Ic9dfa48411f3805747613f03611f8a134a51cc46 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/29017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
135 lines
3.7 KiB
C
135 lines
3.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* cache.c: Cache maintenance routines for ARM64-A and ARM64-R
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*
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* Reference: ARM64 Architecture Reference Manual, ARM64-A and ARM64-R edition
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*/
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#include <stdint.h>
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#include <arch/cache.h>
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#include <arch/lib_helpers.h>
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void tlb_invalidate_all(void)
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{
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/* TLBIALL includes dTLB and iTLB on systems that have them. */
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tlbiall_el2();
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dsb();
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isb();
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}
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enum dcache_op {
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OP_DCCSW,
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OP_DCCISW,
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OP_DCISW,
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OP_DCCIVAC,
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OP_DCCVAC,
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OP_DCIVAC,
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};
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unsigned int dcache_line_bytes(void)
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{
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uint32_t ccsidr;
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static unsigned int line_bytes = 0;
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if (line_bytes)
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return line_bytes;
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ccsidr = raw_read_ccsidr_el1();
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/* [2:0] - Indicates (Log2(number of words in cache line)) - 2 */
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line_bytes = 1 << ((ccsidr & 0x7) + 2); /* words per line */
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line_bytes *= sizeof(unsigned int); /* bytes per word */
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return line_bytes;
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}
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/*
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* Do a dcache operation by virtual address. This is useful for
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* maintaining coherency in drivers which do DMA transfers and only need to
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* perform cache maintenance on a particular memory range rather than the
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* entire cache.
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*/
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static void dcache_op_va(void const *addr, size_t len, enum dcache_op op)
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{
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unsigned long line, linesize;
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linesize = dcache_line_bytes();
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line = (uintptr_t)addr & ~(linesize - 1);
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dsb();
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while (line < (uintptr_t)addr + len) {
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switch(op) {
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case OP_DCCIVAC:
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dccivac(line);
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break;
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case OP_DCCVAC:
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dccvac(line);
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break;
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case OP_DCIVAC:
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dcivac(line);
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break;
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default:
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break;
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}
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line += linesize;
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}
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isb();
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}
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void dcache_clean_by_mva(void const *addr, size_t len)
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{
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dcache_op_va(addr, len, OP_DCCVAC);
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}
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void dcache_clean_invalidate_by_mva(void const *addr, size_t len)
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{
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dcache_op_va(addr, len, OP_DCCIVAC);
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}
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void dcache_invalidate_by_mva(void const *addr, size_t len)
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{
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dcache_op_va(addr, len, OP_DCIVAC);
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}
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void cache_sync_instructions(void)
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{
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uint32_t sctlr = raw_read_sctlr_el2();
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if (sctlr & SCTLR_C)
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dcache_clean_all(); /* includes trailing DSB (assembly) */
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else if (sctlr & SCTLR_I)
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dcache_clean_invalidate_all();
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icache_invalidate_all(); /* includes leading DSB and trailing ISB */
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}
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void arch_program_segment_loaded(void const *addr, size_t len)
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{
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dcache_clean_invalidate_by_mva(addr, len);
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icache_invalidate_all();
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}
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