Benjamin Doron adcb870837 soc/intel/skylake: Configure L1 substates for PCH root ports ...

Exposes PcieRpL1Substates to devicetree to allow boards to override this configuration.

Tested on an Acer Aspire VN7-572G (Skylake-U).

Change-Id: I36150858485715016158595c832c142b0582ddb8
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

2020-10-15 00:01:05 +00:00

..

alderlake

soc/intel/alderlake: Enable TME for Alder Lake

2020-10-14 03:39:00 +00:00

apollolake

soc/intel: Configure PAVP at compile-time

2020-10-12 23:11:04 +00:00

baytrail

src: Rename EM100Pro-specific SPI console Kconfig option

2020-10-13 08:40:52 +00:00

braswell

src: Rename EM100Pro-specific SPI console Kconfig option

2020-10-13 08:40:52 +00:00

broadwell

soc/intel/broadwell/xhci.c: Align with Lynx Point

2020-10-14 08:38:42 +00:00

cannonlake

soc/intel: Configure PAVP at compile-time

2020-10-12 23:11:04 +00:00

common

soc/intel/common/block: Enable PMC IPC driver

2020-10-14 05:37:17 +00:00

denverton_ns

soc/intel/common/block/acpi: Factor out common smbus.asl

2020-10-05 04:00:19 +00:00

elkhartlake

soc/intel: Make use of common gfx.asl

2020-10-08 04:09:46 +00:00

icelake

soc/intel: Configure PAVP at compile-time

2020-10-12 23:11:04 +00:00

jasperlake

soc/intel/jasperlake: Enable CAR NEM enhanced mode

2020-10-14 14:46:59 +00:00

quark

arch/x86: Introduce ARCH_ALL_STAGES_X86_32

2020-09-26 11:42:28 +00:00

skylake

soc/intel/skylake: Configure L1 substates for PCH root ports

2020-10-15 00:01:05 +00:00

tigerlake

soc/intel/tigerlake: Enable and use USB4 PCIe driver

2020-10-14 02:55:35 +00:00

xeon_sp

soc/intel/xeon_sp: Use generic config_t

2020-10-09 20:27:31 +00:00

Kconfig

fsp2_0: Gather Kconfig declarations

2020-04-05 23:26:24 +00:00