add740ac28
Not all devices have a lid switch, so we need to state this somehow. Since the alternative would be to extend get_lid_switch()'s semantics to become a tri-state (open, closed, N/A), do this through Kconfig. BRANCH=none BUG=chromium:446945 TEST=none Change-Id: Icc50f72535f256051a59925a178fb27b2e8f7e55 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d20a1d1a22d64546a5d8761b18ab29732ec0b848 Original-Change-Id: Ie8ac401fbaad5b5a9f1dec2b67847c81f4cc94aa Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/273850 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10692 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
53 lines
886 B
Plaintext
53 lines
886 B
Plaintext
if BOARD_GOOGLE_BOLT
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_INTEL_HASWELL
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select NORTHBRIDGE_INTEL_HASWELL
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select SOUTHBRIDGE_INTEL_LYNXPOINT
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select INTEL_LYNXPOINT_LP
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select BOARD_ROMSIZE_KB_8192
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select EC_GOOGLE_CHROMEEC
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select EC_SOFTWARE_SYNC
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select VIRTUAL_DEV_SWITCH
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_ACPI_RESUME
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select MMCONF_SUPPORT
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select HAVE_SMI_HANDLER
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_LPC_TPM
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select INTEL_INT15
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select CHROMEOS_VBNV_CMOS
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select LID_SWITCH
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config MAINBOARD_DIR
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string
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default google/bolt
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config MAINBOARD_PART_NUMBER
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string
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default "Bolt"
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config MMCONF_BASE_ADDRESS
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hex
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default 0xf0000000
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config MAX_CPUS
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int
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default 8
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config VGA_BIOS_FILE
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string
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default "pci8086,0166.rom"
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config HAVE_IFD_BIN
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bool
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default n
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config HAVE_ME_BIN
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bool
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default n
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endif
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