5888d86868
Add the CPU files required to support the Steppe Eagle and Mullins models of Family 16h SoC processors from AMD. This CPU is based on the Jaguar core and is similar to Kabini. Change-Id: Ib48a3f03128f99a1242fe8c157e0e98feb53b1ea Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6679 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
98 lines
3.1 KiB
C
98 lines
3.1 KiB
C
#ifndef CPU_X86_LAPIC_DEF_H
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#define CPU_X86_LAPIC_DEF_H
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#define LAPIC_BASE_MSR 0x1B
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#define LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR (1 << 8)
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#define LAPIC_BASE_MSR_ENABLE (1 << 11)
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#define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000
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#ifndef LOCAL_APIC_ADDR
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#define LOCAL_APIC_ADDR 0xfee00000
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#endif
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#ifndef LAPIC_DEFAULT_BASE
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#define LAPIC_DEFAULT_BASE LOCAL_APIC_ADDR
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#endif
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#define LAPIC_ID 0x020
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#define LAPIC_LVR 0x030
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#define LAPIC_TASKPRI 0x80
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#define LAPIC_TPRI_MASK 0xFF
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#define LAPIC_ARBID 0x090
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#define LAPIC_RRR 0x0C0
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#define LAPIC_SVR 0x0f0
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#define LAPIC_SPIV 0x0f0
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#define LAPIC_SPIV_ENABLE 0x100
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#define LAPIC_ESR 0x280
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#define LAPIC_ESR_SEND_CS 0x00001
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#define LAPIC_ESR_RECV_CS 0x00002
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#define LAPIC_ESR_SEND_ACC 0x00004
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#define LAPIC_ESR_RECV_ACC 0x00008
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#define LAPIC_ESR_SENDILL 0x00020
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#define LAPIC_ESR_RECVILL 0x00040
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#define LAPIC_ESR_ILLREGA 0x00080
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#define LAPIC_ICR 0x300
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#define LAPIC_DEST_SELF 0x40000
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#define LAPIC_DEST_ALLINC 0x80000
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#define LAPIC_DEST_ALLBUT 0xC0000
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#define LAPIC_ICR_RR_MASK 0x30000
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#define LAPIC_ICR_RR_INVALID 0x00000
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#define LAPIC_ICR_RR_INPROG 0x10000
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#define LAPIC_ICR_RR_VALID 0x20000
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#define LAPIC_INT_LEVELTRIG 0x08000
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#define LAPIC_INT_ASSERT 0x04000
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#define LAPIC_ICR_BUSY 0x01000
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#define LAPIC_DEST_LOGICAL 0x00800
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#define LAPIC_DM_FIXED 0x00000
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#define LAPIC_DM_LOWEST 0x00100
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#define LAPIC_DM_SMI 0x00200
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#define LAPIC_DM_REMRD 0x00300
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#define LAPIC_DM_NMI 0x00400
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#define LAPIC_DM_INIT 0x00500
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#define LAPIC_DM_STARTUP 0x00600
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#define LAPIC_DM_EXTINT 0x00700
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#define LAPIC_VECTOR_MASK 0x000FF
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#define LAPIC_ICR2 0x310
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#define GET_LAPIC_DEST_FIELD(x) (((x)>>24)&0xFF)
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#define SET_LAPIC_DEST_FIELD(x) ((x)<<24)
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#define LAPIC_LVTT 0x320
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#define LAPIC_LVTPC 0x340
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#define LAPIC_LVT0 0x350
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#define LAPIC_LVT_TIMER_BASE_MASK (0x3<<18)
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#define GET_LAPIC_TIMER_BASE(x) (((x)>>18)&0x3)
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#define SET_LAPIC_TIMER_BASE(x) (((x)<<18))
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#define LAPIC_TIMER_BASE_CLKIN 0x0
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#define LAPIC_TIMER_BASE_TMBASE 0x1
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#define LAPIC_TIMER_BASE_DIV 0x2
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#define LAPIC_LVT_TIMER_PERIODIC (1<<17)
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#define LAPIC_LVT_MASKED (1<<16)
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#define LAPIC_LVT_LEVEL_TRIGGER (1<<15)
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#define LAPIC_LVT_REMOTE_IRR (1<<14)
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#define LAPIC_INPUT_POLARITY (1<<13)
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#define LAPIC_SEND_PENDING (1<<12)
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#define LAPIC_LVT_RESERVED_1 (1<<11)
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#define LAPIC_DELIVERY_MODE_MASK (7<<8)
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#define LAPIC_DELIVERY_MODE_FIXED (0<<8)
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#define LAPIC_DELIVERY_MODE_NMI (4<<8)
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#define LAPIC_DELIVERY_MODE_EXTINT (7<<8)
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#define GET_LAPIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
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#define SET_LAPIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8))
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#define LAPIC_MODE_FIXED 0x0
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#define LAPIC_MODE_NMI 0x4
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#define LAPIC_MODE_EXINT 0x7
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#define LAPIC_LVT1 0x360
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#define LAPIC_LVTERR 0x370
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#define LAPIC_TMICT 0x380
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#define LAPIC_TMCCT 0x390
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#define LAPIC_TDCR 0x3E0
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#define LAPIC_TDR_DIV_TMBASE (1<<2)
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#define LAPIC_TDR_DIV_1 0xB
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#define LAPIC_TDR_DIV_2 0x0
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#define LAPIC_TDR_DIV_4 0x1
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#define LAPIC_TDR_DIV_8 0x2
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#define LAPIC_TDR_DIV_16 0x3
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#define LAPIC_TDR_DIV_32 0x8
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#define LAPIC_TDR_DIV_64 0x9
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#define LAPIC_TDR_DIV_128 0xA
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#endif /* CPU_X86_LAPIC_DEF_H */
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