aed887f3cb
CQ-DEPEND=CL:228856 BUG=chrome-os-partner:33676 BRANCH=None TEST=Compiles successfully for samus, link, rush_ryu. Original-Change-Id: I8499cab5dd08981a558688964b99b65d78bde476 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/228743 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit e6aa03752ba8c22b303f3fa590cbc9cf938872ef) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ib229756d8dece6f5670460702413f74bc2c692df Reviewed-on: http://review.coreboot.org/9441 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
162 lines
4.5 KiB
Plaintext
162 lines
4.5 KiB
Plaintext
## This file is part of the coreboot project.
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##
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## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config MAINBOARD_HAS_CHROMEOS
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def_bool n
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menu "ChromeOS"
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depends on MAINBOARD_HAS_CHROMEOS
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config CHROMEOS
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bool "Build for ChromeOS"
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default n
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select TPM
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select BOOTMODE_STRAPS
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help
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Enable ChromeOS specific features like the GPIO sub table in
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the coreboot table. NOTE: Enabling this option on an unsupported
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board will most likely break your build.
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if CHROMEOS
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config VBNV_OFFSET
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hex
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default 0x26
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depends on PC80_SYSTEM
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help
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CMOS offset for VbNv data. This value must match cmos.layout
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in the mainboard directory, minus 14 bytes for the RTC.
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config VBNV_SIZE
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hex
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default 0x10
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depends on PC80_SYSTEM
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help
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CMOS storage size for VbNv data. This value must match cmos.layout
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in the mainboard directory.
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config CHROMEOS_VBNV_CMOS
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bool "Vboot non-volatile storage in CMOS."
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default n
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help
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VBNV is stored in CMOS
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config CHROMEOS_VBNV_EC
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bool "Vboot non-volatile storage in EC."
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default n
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help
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VBNV is stored in EC
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config CHROMEOS_VBNV_FLASH
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def_bool n
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help
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VBNV is stored in flash storage
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config CHROMEOS_RAMOOPS
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bool "Reserve space for Chrome OS ramoops"
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default y
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config CHROMEOS_RAMOOPS_DYNAMIC
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bool "Allocate RAM oops buffer in cbmem"
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default n
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depends on CHROMEOS_RAMOOPS && HAVE_ACPI_TABLES
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config CHROMEOS_RAMOOPS_RAM_START
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hex "Physical address of preserved RAM"
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default 0x00f00000
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depends on CHROMEOS_RAMOOPS && !CHROMEOS_RAMOOPS_DYNAMIC
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config CHROMEOS_RAMOOPS_RAM_SIZE
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hex "Size of preserved RAM"
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default 0x00100000
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depends on CHROMEOS_RAMOOPS
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config FLASHMAP_OFFSET
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hex "Flash Map Offset"
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default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
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default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE
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default 0
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help
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Offset of flash map in firmware image
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config EC_SOFTWARE_SYNC
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bool "Enable EC software sync"
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default n
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depends on VBOOT_VERIFY_FIRMWARE || VBOOT2_VERIFY_FIRMWARE
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help
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EC software sync is a mechanism where the AP helps the EC verify its
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firmware similar to how vboot verifies the main system firmware. This
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option selects whether depthcharge should support EC software sync.
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config VBOOT_EC_SLOW_UPDATE
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bool "EC is slow to update"
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default n
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depends on EC_SOFTWARE_SYNC
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help
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Whether the EC (or PD) is slow to update and needs to display a
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screen that informs the user the update is happening.
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config VBOOT_OPROM_MATTERS
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bool "Video option ROM matters"
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default n
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depends on VBOOT_VERIFY_FIRMWARE
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help
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Whether the video option ROM has run matters on this platform.
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config VIRTUAL_DEV_SWITCH
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bool "Virtual developer switch support"
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default n
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depends on VBOOT_VERIFY_FIRMWARE || VBOOT2_VERIFY_FIRMWARE
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help
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Whether this platform has a virtual developer switch.
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# These VBOOT_X_INDEX are the position of X in FW_MAIN_A/B region. The index
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# table is created by cros_bundle_firmware at build time based on the positions
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# of the blobs listed in fmap.dts and stored at the top of FW_MAIN_A/B region.
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# Unfortunately, there is no programmatical link between the blob list and the
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# index number here.
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config VBOOT_BOOT_LOADER_INDEX
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hex "Bootloader component index"
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default 0
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depends on VBOOT_VERIFY_FIRMWARE || VBOOT2_VERIFY_FIRMWARE
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help
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This is the index of the bootloader component in the verified
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firmware block.
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config VBOOT_RAMSTAGE_INDEX
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hex "Ramstage component index"
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default 1
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depends on VBOOT_VERIFY_FIRMWARE || VBOOT2_VERIFY_FIRMWARE
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help
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This is the index of the ramstage component in the verified
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firmware block.
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config NO_TPM_RESUME
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bool
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default n
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help
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On some boards the TPM stays powered up in S3. On those
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boards, booting Windows will break if the TPM resume command
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is sent during an S3 resume.
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source src/vendorcode/google/chromeos/vboot1/Kconfig
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source src/vendorcode/google/chromeos/vboot2/Kconfig
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endif # CHROMEOS
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endmenu
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