ab69984601
Add support: 1)Support driver rktimer 2)Support driver rkserial BUG=chrome-os-partner:29778 TEST=emerge-veyron libpayload Original-Change-Id: I2cccedf3b62883dd372842a7972e93f2ebbfb282 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206184 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> (cherry picked from commit 387450d7c36b201bd177d46eb9f1d280fc043aab) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia6b7a8ee2439a6f2bf7577df822d3f4f3a1e441c Reviewed-on: http://review.coreboot.org/8127 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
116 lines
2.9 KiB
C
116 lines
2.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Rockchip Electronics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <libpayload-config.h>
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#include <libpayload.h>
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struct rk_uart {
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union {
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u32 uart_thr; /* Transmit holding register. */
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u32 uart_rbr; /* Receive buffer register. */
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u32 uart_dll; /* Divisor latch lsb. */
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};
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union {
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u32 uart_ier; /* Interrupt enable register. */
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u32 uart_dlh; /* Divisor latch msb. */
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};
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union {
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uint32_t uart_iir; /* Interrupt identification register. */
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uint32_t uart_fcr; /* FIFO control register. */
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};
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u32 uart_lcr;
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u32 uart_mcr;
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u32 uart_lsr;
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u32 uart_msr;
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u32 uart_scr;
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u32 reserved1[(0x30 - 0x20) / 4];
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u32 uart_srbr[(0x70 - 0x30) / 4];
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u32 uart_far;
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u32 uart_tfr;
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u32 uart_rfw;
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u32 uart_usr;
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u32 uart_tfl;
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u32 uart_rfl;
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u32 uart_srr;
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u32 uart_srts;
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u32 uart_sbcr;
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u32 uart_sdmam;
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u32 uart_sfe;
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u32 uart_srt;
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u32 uart_stet;
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u32 uart_htx;
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u32 uart_dmasa;
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u32 reserver2[(0xf4 - 0xac) / 4];
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u32 uart_cpr;
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u32 uart_ucv;
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u32 uart_ctr;
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};
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enum {
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UART_LSR_DR = 0x1 << 0, /* Data ready. */
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UART_LSR_OE = 0x1 << 1, /* Overrun. */
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UART_LSR_PE = 0x1 << 2, /* Parity error. */
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UART_LSR_FE = 0x1 << 3, /* Framing error. */
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UART_LSR_BI = 0x1 << 4, /* Break. */
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UART_LSR_THRE = 0x1 << 5, /* Xmit holding register empty. */
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UART_LSR_TEMT = 0x1 << 6, /* Xmitter empty. */
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UART_LSR_ERR = 0x1 << 7 /* Error. */
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};
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static struct rk_uart *uart_regs;
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void serial_putchar(unsigned int c)
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{
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while (!(readl(&uart_regs->uart_lsr) & UART_LSR_THRE));
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writel((c & 0xff), &uart_regs->uart_thr);
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if (c == '\n')
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serial_putchar('\r');
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}
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int serial_havechar(void)
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{
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uint8_t lsr = readl(&uart_regs->uart_lsr);
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return (lsr & UART_LSR_DR) == UART_LSR_DR;
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}
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int serial_getchar(void)
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{
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while (!serial_havechar());
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return readl(&uart_regs->uart_rbr)&0xff;
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}
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static struct console_input_driver consin = {
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.havekey = &serial_havechar,
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.getchar = &serial_getchar
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};
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static struct console_output_driver consout = {.putchar = &serial_putchar
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};
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void serial_init(void)
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{
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if (!lib_sysinfo.serial || !lib_sysinfo.serial->baseaddr)
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return;
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uart_regs = (struct rk_uart *)lib_sysinfo.serial->baseaddr;
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}
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void serial_console_init(void)
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{
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serial_init();
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console_add_input_driver(&consin);
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console_add_output_driver(&consout);
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}
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