aee7ab2f6e
Tested with BUILD_TIMELESS=1, Facebook FBG1701 remains unaffected. Change-Id: I784a5ddc1a8dcbfb960ce970b28b850244a47773 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39663 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
175 lines
4.7 KiB
C
175 lines
4.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* The devicetree parser expects chip.h to reside directly in the path
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* specified by the devicetree.
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*/
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#ifndef _SOC_CHIP_H_
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#define _SOC_CHIP_H_
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#include <stdint.h>
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#include <fsp/util.h>
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#include <intelblocks/lpc_lib.h>
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#include <soc/pci_devs.h>
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#include <smbios.h>
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#define SVID_CONFIG1 1
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#define SVID_CONFIG3 3
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#define SVID_PMIC_CONFIG 8
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#define IGD_MEMSIZE_32MB 0x01
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#define IGD_MEMSIZE_64MB 0x02
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#define IGD_MEMSIZE_96MB 0x03
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#define IGD_MEMSIZE_128MB 0x04
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enum lpe_clk_src {
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LPE_CLK_SRC_XTAL,
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LPE_CLK_SRC_PLL,
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};
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enum usb_comp_bg_value {
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USB_COMP_BG_575_MV = 7,
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USB_COMP_BG_650_MV = 6,
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USB_COMP_BG_550_MV = 5,
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USB_COMP_BG_537_MV = 4,
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USB_COMP_BG_625_MV = 3,
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USB_COMP_BG_700_MV = 2,
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USB_COMP_BG_600_MV = 1,
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USB_COMP_BG_675_MV = 0,
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};
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struct soc_intel_braswell_config {
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uint8_t enable_xdp_tap;
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uint8_t clkreq_enable;
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enum serirq_mode serirq_mode;
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/* Disable SLP_X stretching after SUS power well loss */
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int disable_slp_x_stretch_sus_fail;
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/* LPE Audio Clock configuration */
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enum lpe_clk_src lpe_codec_clk_src; /* Both are 19.2MHz */
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/* Native SD Card controller - override controller capabilities */
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uint32_t sdcard_cap_low;
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uint32_t sdcard_cap_high;
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/* Enable devices in ACPI mode */
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int lpss_acpi_mode;
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int emmc_acpi_mode;
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int sd_acpi_mode;
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int lpe_acpi_mode;
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/* Allow PCIe devices to wake system from suspend */
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int pcie_wake_enable;
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/* Program USB2_COMPBG register.
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* [10:7] - select vref to AFE port
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* x111 - 575mV, x110 - 650mV, x101 - 550mV, x100 - 537.5mV,
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* x011 - 625mV, x010 - 700mV, x001 - 600mV, x000 - 675mV
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*/
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enum usb_comp_bg_value usb_comp_bg;
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/*
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* The following fields come from fsp_vpd.h .aka. VpdHeader.h.
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* These are configuration values that are passed to FSP during MemoryInit.
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*/
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uint16_t PcdMrcInitTsegSize;
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uint16_t PcdMrcInitMmioSize;
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uint8_t PcdMrcInitSpdAddr1;
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uint8_t PcdMrcInitSpdAddr2;
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uint8_t PcdIgdDvmt50PreAlloc;
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uint8_t PcdApertureSize;
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uint8_t PcdGttSize;
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uint8_t PcdLegacySegDecode;
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uint8_t PcdDvfsEnable;
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uint8_t PcdCaMirrorEn; /* Command Address Mirroring Enabled */
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/*
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* The following fields come from fsp_vpd.h .aka. VpdHeader.h.
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* These are configuration values that are passed to FSP during SiliconInit.
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*/
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uint8_t PcdSdcardMode;
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uint8_t PcdEnableHsuart0;
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uint8_t PcdEnableHsuart1;
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uint8_t PcdEnableAzalia;
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uint8_t PcdEnableSata;
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uint8_t PcdEnableXhci;
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uint8_t PcdEnableLpe;
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uint8_t PcdEnableDma0;
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uint8_t PcdEnableDma1;
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uint8_t PcdEnableI2C0;
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uint8_t PcdEnableI2C1;
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uint8_t PcdEnableI2C2;
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uint8_t PcdEnableI2C3;
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uint8_t PcdEnableI2C4;
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uint8_t PcdEnableI2C5;
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uint8_t PcdEnableI2C6;
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uint8_t PunitPwrConfigDisable;
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uint8_t ChvSvidConfig;
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uint8_t DptfDisable;
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uint8_t PcdEmmcMode;
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uint8_t PcdUsb3ClkSsc;
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uint8_t PcdDispClkSsc;
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uint8_t PcdSataClkSsc;
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uint8_t Usb2Port0PerPortPeTxiSet;
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uint8_t Usb2Port0PerPortTxiSet;
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uint8_t Usb2Port0IUsbTxEmphasisEn;
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uint8_t Usb2Port0PerPortTxPeHalf;
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uint8_t Usb2Port1PerPortPeTxiSet;
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uint8_t Usb2Port1PerPortTxiSet;
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uint8_t Usb2Port1IUsbTxEmphasisEn;
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uint8_t Usb2Port1PerPortTxPeHalf;
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uint8_t Usb2Port2PerPortPeTxiSet;
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uint8_t Usb2Port2PerPortTxiSet;
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uint8_t Usb2Port2IUsbTxEmphasisEn;
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uint8_t Usb2Port2PerPortTxPeHalf;
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uint8_t Usb2Port3PerPortPeTxiSet;
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uint8_t Usb2Port3PerPortTxiSet;
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uint8_t Usb2Port3IUsbTxEmphasisEn;
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uint8_t Usb2Port3PerPortTxPeHalf;
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uint8_t Usb2Port4PerPortPeTxiSet;
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uint8_t Usb2Port4PerPortTxiSet;
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uint8_t Usb2Port4IUsbTxEmphasisEn;
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uint8_t Usb2Port4PerPortTxPeHalf;
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uint8_t Usb3Lane0Ow2tapgen2deemph3p5;
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uint8_t Usb3Lane1Ow2tapgen2deemph3p5;
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uint8_t Usb3Lane2Ow2tapgen2deemph3p5;
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uint8_t Usb3Lane3Ow2tapgen2deemph3p5;
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uint8_t PcdSataInterfaceSpeed;
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uint8_t PcdPchUsbSsicPort;
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uint8_t PcdPchUsbHsicPort;
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uint8_t PcdPcieRootPortSpeed;
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uint8_t PcdPchSsicEnable;
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uint32_t PcdLogoPtr;
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uint32_t PcdLogoSize;
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uint8_t PcdRtcLock;
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uint8_t PMIC_I2CBus;
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uint8_t ISPEnable;
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uint8_t ISPPciDevConfig;
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uint8_t PcdSdDetectChk; /* Enable / Disable SD Card Detect Simulation */
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uint8_t I2C0Frequency; /* 0 - 100KHz, 1 - 400KHz, 2 - 1MHz */
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uint8_t I2C1Frequency;
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uint8_t I2C2Frequency;
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uint8_t I2C3Frequency;
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uint8_t I2C4Frequency;
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uint8_t I2C5Frequency;
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uint8_t I2C6Frequency;
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};
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#endif /* _SOC_CHIP_H_ */
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