af4bd5633d
Retype the `pcie_port_coalesce` devicetree options and related variables to better reflect their bivalue (boolean) nature. Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
79 lines
1.6 KiB
C
79 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _SOC_INTEL_BROADWELL_PCH_CHIP_H_
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#define _SOC_INTEL_BROADWELL_PCH_CHIP_H_
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#include <types.h>
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struct soc_intel_broadwell_pch_config {
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/* GPE configuration */
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uint32_t gpe0_en_1;
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uint32_t gpe0_en_2;
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uint32_t gpe0_en_3;
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uint32_t gpe0_en_4;
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/* GPIO SMI configuration */
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uint32_t alt_gp_smi_en;
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/* IDE configuration */
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uint8_t sata_port_map;
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uint32_t sata_port0_gen3_tx;
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uint32_t sata_port1_gen3_tx;
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uint32_t sata_port2_gen3_tx;
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uint32_t sata_port3_gen3_tx;
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uint32_t sata_port0_gen3_dtle;
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uint32_t sata_port1_gen3_dtle;
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uint32_t sata_port2_gen3_dtle;
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uint32_t sata_port3_gen3_dtle;
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/*
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* SATA DEVSLP Mux
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* 0 = port 0 DEVSLP on DEVSLP0/GPIO33
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* 1 = port 3 DEVSLP on DEVSLP0/GPIO33
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*/
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uint8_t sata_devslp_mux;
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/*
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* DEVSLP Disable
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* 0: DEVSLP is enabled
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* 1: DEVSLP is disabled
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*/
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uint8_t sata_devslp_disable;
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/* Generic IO decode ranges */
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uint32_t gen1_dec;
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uint32_t gen2_dec;
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uint32_t gen3_dec;
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uint32_t gen4_dec;
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/* Enable linear PCIe Root Port function numbers starting at zero */
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bool pcie_port_coalesce;
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/* Force root port ASPM configuration with port bitmap */
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uint8_t pcie_port_force_aspm;
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/* Put SerialIO devices into ACPI mode instead of a PCI device */
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uint8_t sio_acpi_mode;
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/* I2C voltage select: 0=3.3V 1=1.8V */
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uint8_t sio_i2c0_voltage;
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uint8_t sio_i2c1_voltage;
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/* Enable ADSP power gating features */
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uint8_t adsp_d3_pg_enable;
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uint8_t adsp_sram_pg_enable;
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/*
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* Clock Disable Map:
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* [21:16] = CLKOUT_PCIE# 5-0
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* [24] = CLKOUT_ITPXDP
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*/
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uint32_t icc_clock_disable;
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/* Deep SX enable */
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int deep_sx_enable_ac;
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int deep_sx_enable_dc;
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};
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#endif
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