b0dd1d91f4
Change-Id: I8e80c22eb0f3cb68f2457be6b2e7894df60ed632 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/822 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
132 lines
3.8 KiB
C
132 lines
3.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/romcc_io.h>
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#include <device/pnp_def.h>
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#include "it8772f.h"
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/* The base address is 0x2e or 0x4e, depending on config bytes. */
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#define SIO_BASE IT8772F_BASE
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#define SIO_INDEX SIO_BASE
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#define SIO_DATA (SIO_BASE + 1)
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/* Global configuration registers. */
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#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
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#define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
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#define IT8772F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
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#define IT8772F_CONFIG_REG_MFC 0x2a /* Multi-function control */
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#define IT8772F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
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u8 it8772f_sio_read(u8 index)
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{
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outb(index, SIO_BASE);
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return inb(SIO_DATA);
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}
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void it8772f_sio_write(u8 index, u8 value)
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{
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outb(index, SIO_BASE);
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outb(value, SIO_DATA);
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}
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static void it8772f_enter_conf(void)
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{
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u16 port = SIO_BASE;
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outb(0x87, port);
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outb(0x01, port);
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outb(0x55, port);
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outb((port == 0x4e) ? 0xaa : 0x55, port);
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}
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static void it8772f_exit_conf(void)
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{
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it8772f_sio_write(IT8772F_CONFIG_REG_CC, 0x02);
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}
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/* Select 24MHz CLKIN (48MHz is the default). */
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void it8772f_24mhz_clkin(void)
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{
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it8772f_enter_conf();
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it8772f_sio_write(IT8772F_CONFIG_REG_LDN, 0x00);
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it8772f_sio_write(IT8772F_CONFIG_REG_CLOCKSEL, 0x1);
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it8772f_exit_conf();
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}
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/*
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* LDN 7, reg 0x2a - needed for S3, or memory power will be cut off.
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*
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* Enable 3VSBSW#. (For System Suspend-to-RAM)
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* 0: 3VSBSW# will be always inactive.
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* 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#.
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*/
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void it8772f_enable_3vsbsw(void)
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{
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it8772f_enter_conf();
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it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
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it8772f_sio_write(IT8772F_CONFIG_REG_MFC, 0x80);
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it8772f_exit_conf();
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}
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void it8772f_kill_watchdog(void)
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{
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it8772f_enter_conf();
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it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
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it8772f_sio_write(IT8772F_CONFIG_REG_WATCHDOG, 0x00);
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it8772f_exit_conf();
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}
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/* Enable the serial port(s). */
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void it8772f_enable_serial(device_t dev, u16 iobase)
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{
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it8772f_enter_conf();
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it8772f_sio_write(IT8772F_CONFIG_REG_LDN, dev & 0xff);
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it8772f_sio_write(PNP_IDX_IO0, (iobase >> 8) & 0xff);
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it8772f_sio_write(PNP_IDX_IO0+1, iobase & 0xff);
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it8772f_sio_write(PNP_IDX_EN, 1);
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it8772f_exit_conf();
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}
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/* Set AC resume to be up to the Southbridge */
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void it8772f_ac_resume_southbridge(void)
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{
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it8772f_enter_conf();
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it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_EC);
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it8772f_sio_write(0xf4, 0x60);
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it8772f_exit_conf();
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}
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/* Configure a set of GPIOs */
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void it8772f_gpio_setup(int set, u8 select, u8 polarity, u8 pullup,
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u8 output, u8 enable)
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{
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set--; /* Set 1 is offset 0 */
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it8772f_enter_conf();
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it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
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if (set < 5) {
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it8772f_sio_write(GPIO_REG_SELECT(set), select);
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it8772f_sio_write(GPIO_REG_ENABLE(set), enable);
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it8772f_sio_write(GPIO_REG_POLARITY(set), polarity);
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}
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it8772f_sio_write(GPIO_REG_OUTPUT(set), output);
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it8772f_sio_write(GPIO_REG_PULLUP(set), pullup);
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it8772f_exit_conf();
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}
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