b30e2bfe34
Only bus_sp5100[0] is evaluated. Change-Id: I42a5040ea70a84fb674f2c616c6eba7b23dcdc29 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
134 lines
4.7 KiB
C
134 lines
4.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/smp/mpspec.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <string.h>
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#include <stdint.h>
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#include <cpu/amd/amdfam10_sysconf.h>
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extern u8 bus_sr5650[14];
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extern u32 apicid_sp5100;
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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int bus_isa;
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u32 apicid_sr5650;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, LOCAL_APIC_ADDR);
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smp_write_processors(mc);
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apicid_sp5100 = 0x20;
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apicid_sr5650 = apicid_sp5100 + 1;
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mptable_write_buses(mc, NULL, &bus_isa);
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/* I/O APICs: APIC ID Version State Address */
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{
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struct device *dev;
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u32 *dword;
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u8 byte;
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dev = dev_find_slot(0, //pirq_router_bus TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0.
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PCI_DEVFN(0x14, 0));
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if (dev) {
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dword = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0);
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smp_write_ioapic(mc, apicid_sp5100, 0x11, dword);
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/* Initialize interrupt mapping */
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/* aza */
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byte = pci_read_config8(dev, 0x63);
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byte &= 0xf8;
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byte |= 0; /* 0: INTA, ...., 7: INTH */
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pci_write_config8(dev, 0x63, byte);
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/* SATA */
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dword = (u32 *)((pci_read_config32(dev, 0xac) &
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~(7 << 26)) | (6 << 26));
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/* dword |= 1 << 22; PIC and APIC co exists */
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pci_write_config32(dev, 0xac, (u32)dword);
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/*
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* 00:12.0: PROG SATA : INT F
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* 00:13.0: INTA USB_0
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* 00:13.1: INTB USB_1
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* 00:13.2: INTC USB_2
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* 00:13.3: INTD USB_3
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* 00:13.4: INTC USB_4
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* 00:13.5: INTD USB2
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* 00:14.1: INTA IDE
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* 00:14.2: Prog HDA : INT E
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* 00:14.5: INTB ACI
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* 00:14.6: INTB MCI
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*/
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}
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dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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if (dev) {
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pci_write_config32(dev, 0xF8, 0x1);
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dword = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
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smp_write_ioapic(mc, apicid_sp5100+1, 0x11, dword);
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}
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}
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/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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#define IO_LOCAL_INT(type, intr, apicid, pin) \
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smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
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mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0);
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/* on board NIC & Slot PCIE. */
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/* configuration B doesnt need dev 5,6,7 */
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/*
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* PCI_INT(bus_sr5650[0x5], 0x0, 0x0, 0x11);
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* PCI_INT(bus_sr5650[0x6], 0x0, 0x0, 0x12);
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* PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13);
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*/
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((2)<<2)|(0)), apicid_sp5100+1, 28); /* dev 2 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((4)<<2)|(0)), apicid_sp5100+1, 28); /* dev 4 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sp5100+1, 30); /* dev 11 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sp5100+1, 30); /* dev 12 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[2], (((0)<<2)|(0)), apicid_sp5100+1, 0); /* card behind dev2 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[4], (((0)<<2)|(0)), apicid_sp5100+1, 20);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[4], (((0)<<2)|(1)), apicid_sp5100+1, 21); /* NIC */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[11], (((0)<<2)|(0)), apicid_sp5100+1, 8);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[11], (((0)<<2)|(1)), apicid_sp5100+1, 9); /* card behind dev11 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[12], (((0)<<2)|(0)), apicid_sp5100+1, 12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[12], (((0)<<2)|(1)), apicid_sp5100+1, 13); /* card behind dev12 */
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/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
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IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
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/* There is no extension information... */
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/* Compute the checksums */
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return mptable_finalize(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr, 0);
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return (unsigned long)smp_write_config_table(v);
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}
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