b36100faf4
For consistency with other platforms, use `SOC_INTEL_GEMINILAKE`. Change-Id: I06310e5a9bca6c9504f19a6c2fe9b26626f290d4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
112 lines
2.9 KiB
C
112 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <bootblock_common.h>
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#include <cpu/x86/pae.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/p2sb.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/rtc.h>
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#include <intelblocks/systemagent.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/tco.h>
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#include <intelblocks/uart.h>
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#include <soc/iomap.h>
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#include <soc/cpu.h>
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#include <soc/gpio.h>
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#include <soc/systemagent.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <spi-generic.h>
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static const struct pad_config tpm_spi_configs[] = {
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#if CONFIG(SOC_INTEL_GEMINILAKE)
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PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */
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#else
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PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */
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#endif
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};
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static void tpm_enable(void)
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{
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/* Configure gpios */
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gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs));
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}
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asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
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{
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pci_devfn_t dev;
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bootblock_systemagent_early_init();
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p2sb_enable_bar();
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p2sb_configure_hpet();
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/* Decode the ACPI I/O port range for early firmware verification.*/
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dev = PCH_DEV_PMC;
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pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_BASE_ADDRESS);
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pci_write_config16(dev, PCI_COMMAND,
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PCI_COMMAND_IO | PCI_COMMAND_MASTER);
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enable_rtc_upper_bank();
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/* Call lib/bootblock.c main */
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bootblock_main_with_basetime(base_timestamp);
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}
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static void enable_pmcbar(void)
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{
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pci_devfn_t pmc = PCH_DEV_PMC;
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/* Set PMC base addresses and enable decoding. */
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pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0);
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pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */
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pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1);
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pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */
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pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_BASE_ADDRESS);
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pci_write_config16(pmc, PCI_COMMAND,
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER);
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}
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void bootblock_soc_early_init(void)
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{
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enable_pmcbar();
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/* Clear global reset promotion bit */
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pmc_global_reset_enable(0);
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/* Prepare UART for serial console. */
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if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
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uart_bootblock_init();
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if (CONFIG(DRIVERS_UART_8250IO))
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lpc_io_setup_comm_a_b();
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if (CONFIG(TPM_ON_FAST_SPI))
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tpm_enable();
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enable_pm_timer_emulation();
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fast_spi_early_init(SPI_BASE_ADDRESS);
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fast_spi_cache_bios_region();
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/* Initialize GPE for use as interrupt status */
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pmc_gpe_init();
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/* Program TCO Timer Halt */
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tco_configure();
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/* Use Nx and paging to prevent the frontend from writing back dirty
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* cache-as-ram lines to backing store that doesn't exist when the L1I
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* speculatively fetches a line that is sitting in the L1D. */
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if (CONFIG(PAGING_IN_CACHE_AS_RAM)) {
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paging_set_nxe(1);
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paging_set_default_pat();
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paging_enable_for_car("pdpt", "pt");
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}
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}
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