b3f2323e84
This is a merely cosmetic change. Change-Id: If36419fbee9628b591116604bf32fe00a4f08c17 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
110 lines
3.6 KiB
Plaintext
110 lines
3.6 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip northbridge/intel/sandybridge
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register "gfx.ndid" = "3"
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register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
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device cpu_cluster 0x0 on
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chip cpu/intel/socket_LGA1155
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device lapic 0x0 on end
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end
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chip cpu/intel/model_206ax
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register "c1_acpower" = "1"
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register "c1_battery" = "1"
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register "c2_acpower" = "3"
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register "c2_battery" = "3"
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register "c3_acpower" = "5"
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register "c3_battery" = "5"
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device lapic 0xacac off end
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end
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end
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register "pci_mmio_size" = "2048"
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device domain 0x0 on
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "c2_latency" = "0x0065"
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register "docking_supported" = "0"
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register "gen1_dec" = "0x003c0a01"
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register "p_cnt_throttling_supported" = "0"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_port_map" = "0x33"
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register "spi_lvscc" = "0x2005"
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register "spi_uvscc" = "0x2005"
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 19.0 off end # Intel Gigabit Ethernet
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device pci 1a.0 on end # USB2 EHCI #2
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device pci 1b.0 on end # High Definition Audio Audio controller
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device pci 1c.0 on end # PCIe x1 Port (PCIEX1)
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device pci 1c.1 off end # Unused PCIe Port
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device pci 1c.2 off end # Unused PCIe Port
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device pci 1c.3 off end # Unused PCIe Port
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device pci 1c.4 on end # Realtek RTL8111F Ethernet Controller
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device pci 1c.5 on end # ITE IT8892F PCIe to PCI bridge
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device pci 1c.6 off end # Unused PCIe Port
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device pci 1c.7 off end # Unused PCIe Port
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device pci 1d.0 on end # USB2 EHCI #1
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device pci 1e.0 on end # PCI bridge
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device pci 1f.0 on # LPC bridge
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chip superio/ite/it8728f
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device pnp 2e.0 off end # Floppy, not routed.
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device pnp 2e.1 on # COM1
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io 0x60 = 0x03f8
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irq 0x70 = 4
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end
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device pnp 2e.2 off end # COM2, not routed.
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device pnp 2e.3 on # Parallel port
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io 0x60 = 0x0378
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irq 0x70 = 7
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drq 0x74 = 4
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end
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device pnp 2e.4 on # Environment Controller
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io 0x60 = 0x0a30
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irq 0x70 = 9
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io 0x62 = 0x0a20
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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irq 0x70 = 1
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io 0x62 = 0x64
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end
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device pnp 2e.6 on # Mouse
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irq 0x70 = 12
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end
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device pnp 2e.7 off # GPIO
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io 0x25 = 0x40
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io 0x27 = 0x10
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io 0x2c = 0x80
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io 0x62 = 0x0a00
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io 0xcb = 0x00
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io 0xf1 = 0x40
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end
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device pnp 2e.a off end # CIR, not routed.
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end
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end
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device pci 1f.2 on end # SATA Controller 1
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device pci 1f.3 on end # SMBus
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device pci 1f.5 off end # SATA Controller 2
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device pci 1f.6 off end # Thermal
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end
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device pci 00.0 on end # Host bridge
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device pci 01.0 on end # PCIe Bridge for discrete graphics (PCIEX16)
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device pci 02.0 on end # Internal graphics VGA controller
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end
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end
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