b42ca4d0b2
When enabled, the EC will mirror the firmware contained inside the coreboot ROM. This allows it to be updated at the same time as coreboot. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ief088e012b65be32648f581fc3190e1000bca241 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
108 lines
3.2 KiB
C
108 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* EC communication interface for Embedded Controller.
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*/
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#ifndef _EC_STARLABS_EC_H
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#define _EC_STARLABS_EC_H
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/*
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* Define the expected value of the PNP base address that is fixed through
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* the BADRSEL register controlled within the EC domain by the EC Firmware.
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*/
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#define ITE_FIXED_ADDR 0x4e
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#define NUVOTON_FIXED_ADDR 0x4e
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/* Logical device number (LDN) assignments for ITE. */
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#define ITE_SP1 0x01 /* Serial Port 1 (UART) */
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#define ITE_SP2 0x02 /* Serial Port 2 (UART) */
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#define ITE_SWUC 0x04 /* System Wake-Up Control (SWUC) */
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#define ITE_KBCM 0x05 /* KBC / Mouse Interface */
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#define ITE_KBCK 0x06 /* KBC / Keyboard Interface */
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#define ITE_IR 0x0a /* Consumer IR (CIR) */
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#define ITE_SMFI 0x0f /* Shared Memory / Flash Interface (SMFI) */
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#define ITE_RTCT 0x10 /* RTC-like Timer (RCTC) */
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#define ITE_PMC1 0x11 /* Power Management I/F Channel 1 (PMC1) */
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#define ITE_PMC2 0x12 /* Power Management I/F Channel 2 (PMC2) */
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#define ITE_SSPI 0x13 /* Serial Peripheral Interface (SSPI) */
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#define ITE_PECI 0x14 /* Platform Environment Control Interface (PECI) */
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#define ITE_PMC3 0x17 /* Power Management I/F Channel 3 (PMC3) */
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#define ITE_PMC4 0x18 /* Power Management I/F Channel 4 (PMC4) */
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#define ITE_PMC5 0x19 /* Power Management I/F Channel 5 (PMC5) */
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/* Logical device number (LDN) assignments for Nuvoton. */
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#define NUVOTON_MSWC 0x04 /* Mobile System Wake-Up Control (MSWC) */
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#define NUVOTON_KBCM 0x05 /* KBC / Mouse Interface */
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#define NUVOTON_KBCK 0x06 /* KBC / Keyboard Interface */
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#define NUVOTON_SHM 0x0f /* Shared Memory (SHM) */
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#define NUVOTON_PM1 0x11 /* Power Management I/F Channel 1 (PM1) */
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#define NUVOTON_PM2 0x12 /* Power Management I/F Channel 2 (PM2) */
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#define NUVOTON_PM3 0x17 /* Power Management I/F Channel 3 (PM3) */
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#define NUVOTON_ESHM 0x1d /* Extended Shared Memory (ESHM) */
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#define NUVOTON_PM4 0x1e /* Power Management I/F Channel 3 (PM4) */
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/* Host domain registers. */
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#define ITE_CHIPID1 0x20 /* Device ID register 1 */
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#define ITE_CHIPID2 0x21 /* Device ID register 2 */
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#define NUVOTON_CHIPID 0x27 /* Device ID register */
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/* EC RAM common offsets */
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#define ECRAM_MAJOR_VERSION 0x00
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#define ECRAM_MINOR_VERSION 0x01
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/*
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* CMOS Settings
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*/
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/* Keyboard Backlight Timeout */
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#define SEC_30 0x00
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#define MIN_1 0x01
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#define MIN_3 0x02
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#define MIN_5 0x03
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#define NEVER 0x04
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/* Fn Ctrl Swap */
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#define FN_CTRL 0x00
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#define CTRL_FN 0x01
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/* Max Charge Setting */
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#define CHARGE_100 0x00
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#define CHARGE_80 0xbb
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#define CHARGE_60 0xaa
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/* Fast Charge Setting */
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#define CHARGE_RATE_NORMAL 0x00
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#define CHARGE_RATE_FAST 0x01
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/* Fan Mode Setting */
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#define FAN_NORMAL 0x00
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#define FAN_AGGRESSIVE 0xbb
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#define FAN_QUIET 0xaa
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/* Fn Lock State */
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#define UNLOCKED 0x00
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#define LOCKED 0x01
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/* Trackpad State */
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#define TRACKPAD_ENABLED 0x00
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#define TRACKPAD_DISABLED 0x22
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/* Keyboard Brightness Levels */
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#define KBL_ON 0xdd
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#define KBL_OFF 0xcc
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#define KBL_LOW 0xbb
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#define KBL_HIGH 0xaa
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/* Keyboard Backlight State */
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#define KBL_DISABLED 0x00
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#define KBL_ENABLED 0xdd
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/* Mirror Flag */
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#define MIRROR_DISABLED 0x00
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#define MIRROR_ENABLED 0x01
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uint16_t ec_get_version(void);
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#endif
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