b48d63359b
This common implementation is compatible. Change-Id: I2023bb7522ec40f1d9911cb5c57d7d66e4cefa6d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
180 lines
4.1 KiB
Plaintext
180 lines
4.1 KiB
Plaintext
config SOC_INTEL_BAYTRAIL
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bool
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help
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Bay Trail M/D part support.
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if SOC_INTEL_BAYTRAIL
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_VERSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select BOOT_DEVICE_SUPPORTS_WRITES
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select CACHE_MRC_SETTINGS
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select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
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select SUPPORT_CPU_UCODE_IN_CBFS
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select HAVE_SMI_HANDLER
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select SOUTHBRIDGE_INTEL_COMMON_RESET
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select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
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select NO_FIXED_XIP_ROM_SIZE
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select PARALLEL_MP
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select PCIEXP_ASPM
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select PCIEXP_COMMON_CLOCK
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select REG_SCRIPT
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select RTC
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select SMP
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select SPI_FLASH
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select SSE2
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select TSC_MONOTONIC_TIMER
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select TSC_SYNC_MFENCE
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select UDELAY_TSC
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select SOC_INTEL_COMMON
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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select HAVE_SPI_CONSOLE_SUPPORT
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select INTEL_GMA_ACPI
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select INTEL_GMA_SWSMISCI
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select CPU_INTEL_COMMON
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select CPU_HAS_L2_ENABLE_MSR
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select ROMCC_BOOTBLOCK
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config VBOOT
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select VBOOT_MUST_REQUEST_DISPLAY
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select VBOOT_STARTS_IN_ROMSTAGE
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config BOOTBLOCK_CPU_INIT
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string
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default "soc/intel/baytrail/bootblock/bootblock.c"
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config MMCONF_BASE_ADDRESS
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hex
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default 0xe0000000
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config MAX_CPUS
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int
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default 4
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config CPU_ADDR_BITS
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int
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default 36
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config SMM_TSEG_SIZE
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hex
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default 0x800000
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config SMM_RESERVED_SIZE
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hex
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default 0x100000
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config HAVE_MRC
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bool "Add a System Agent binary"
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help
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Select this option to add a System Agent binary to
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the resulting coreboot image.
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Note: Without this binary coreboot will not work
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config MRC_FILE
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string "Intel System Agent path and filename"
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depends on HAVE_MRC
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default "mrc.bin"
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help
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The path and filename of the file to use as System Agent
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binary.
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config MRC_BIN_ADDRESS
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hex
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default 0xfffa0000
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config MRC_RMT
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bool "Enable MRC RMT training + debug prints"
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default n
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# Cache As RAM region layout:
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#
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# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE
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# | MRC usage |
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# | |
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# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE
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# | Stack |
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# | | |
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# | v |
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# +-------------+
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# | ^ |
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# | | |
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# | CAR Globals |
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# +-------------+ DCACHE_RAM_BASE
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#
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# Note that the MRC binary is linked to assume the region marked as "MRC usage"
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# starts at DCACHE_RAM_BASE + DCACHE_RAM_SIZE. If those values change then
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# a new MRC binary needs to be produced with the updated start and size
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# information.
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config DCACHE_RAM_BASE
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hex
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default 0xfe000000
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config DCACHE_RAM_SIZE
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hex
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default 0x8000
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
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must add up to a power of 2.
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config DCACHE_RAM_MRC_VAR_SIZE
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hex
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default 0x8000
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help
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The amount of cache-as-ram region required by the reference code.
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config RESET_ON_INVALID_RAMSTAGE_CACHE
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bool "Reset the system on S3 wake when ramstage cache invalid."
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default n
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help
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The baytrail romstage code caches the loaded ramstage program
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in SMM space. On S3 wake the romstage will copy over a fresh
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ramstage that was cached in the SMM space. This option determines
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the action to take when the ramstage cache is invalid. If selected
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the system will reset otherwise the ramstage will be reloaded from
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cbfs.
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config ENABLE_BUILTIN_COM1
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bool "Enable builtin COM1 Serial Port"
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default n
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help
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The PMC has a legacy COM1 serial port. Choose this option to
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configure the pads and enable it. This serial port can be used for
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the debug console.
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config HAVE_REFCODE_BLOB
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depends on ARCH_X86
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bool "An external reference code blob should be put into cbfs."
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default n
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help
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The reference code blob will be placed into cbfs.
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if HAVE_REFCODE_BLOB
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config REFCODE_BLOB_FILE
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string "Path and filename to reference code blob."
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default "refcode.elf"
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help
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The path and filename to the file to be added to cbfs.
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endif # HAVE_REFCODE_BLOB
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config VGA_BIOS_ID
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string
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depends on VGA_BIOS
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default "8086,0f31"
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config VGA_BIOS_FILE
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string
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depends on VGA_BIOS
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default "pci8086,0f31.rom"
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endif
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