b5828d7445
the information is already specified in cmos.layout. coreboot is changed to use that version instead. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmai.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
118 lines
2.0 KiB
Plaintext
118 lines
2.0 KiB
Plaintext
config BOARD_NVIDIA_L1_2PVV
|
|
bool "l1_2pvv"
|
|
select ARCH_X86
|
|
select CPU_AMD_SOCKET_F
|
|
select NORTHBRIDGE_AMD_AMDK8
|
|
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
|
|
select SOUTHBRIDGE_NVIDIA_MCP55
|
|
select SUPERIO_WINBOND_W83627EHG
|
|
select HAVE_BUS_CONFIG
|
|
select HAVE_PIRQ_TABLE
|
|
select HAVE_MP_TABLE
|
|
select USE_PRINTK_IN_CAR
|
|
select USE_DCACHE_RAM
|
|
select HAVE_HARD_RESET
|
|
select LIFT_BSP_APIC_ID
|
|
select K8_REV_F_SUPPORT
|
|
select BOARD_ROMSIZE_KB_512
|
|
|
|
config MAINBOARD_DIR
|
|
string
|
|
default nvidia/l1_2pvv
|
|
depends on BOARD_NVIDIA_L1_2PVV
|
|
|
|
config DCACHE_RAM_BASE
|
|
hex
|
|
default 0xc8000
|
|
depends on BOARD_NVIDIA_L1_2PVV
|
|
|
|
config DCACHE_RAM_SIZE
|
|
hex
|
|
default 0x08000
|
|
depends on BOARD_NVIDIA_L1_2PVV
|
|
|
|
config DCACHE_RAM_GLOBAL_VAR_SIZE
|
|
hex
|
|
default 0x01000
|
|
depends on BOARD_NVIDIA_L1_2PVV
|
|
|
|
config APIC_ID_OFFSET
|
|
hex
|
|
default 0x10
|
|
depends on BOARD_NVIDIA_L1_2PVV
|
|
|
|
config MEM_TRAIN_SEQ
|
|
int
|
|
default 1
|
|
depends on BOARD_NVIDIA_L1_2PVV
|
|
|
|
config SB_HT_CHAIN_ON_BUS0
|
|
int
|
|
default 2
|
|
depends on BOARD_NVIDIA_L1_2PVV
|
|
|
|
config MAINBOARD_PART_NUMBER
|
|
string
|
|
default "l1_2pvv"
|
|
depends on BOARD_NVIDIA_L1_2PVV
|
|
|
|
config PCI_64BIT_PREF_MEM
|
|
bool
|
|
default n
|
|
depends on BOARD_NVIDIA_L1_2PVV
|
|
|
|
config HW_MEM_HOLE_SIZEK
|
|
hex
|
|
default 0x100000
|
|
depends on BOARD_NVIDIA_L1_2PVV
|
|
|
|
config MAX_CPUS
|
|
int
|
|
default 4
|
|
depends on BOARD_NVIDIA_L1_2PVV
|
|
|
|
config MAX_PHYSICAL_CPUS
|
|
int
|
|
default 2
|
|
depends on BOARD_NVIDIA_L1_2PVV
|
|
|
|
config HW_MEM_HOLE_SIZE_AUTO_INC
|
|
bool
|
|
default n
|
|
depends on BOARD_NVIDIA_L1_2PVV
|
|
|
|
config HT_CHAIN_UNITID_BASE
|
|
hex
|
|
default 0x0
|
|
depends on BOARD_NVIDIA_L1_2PVV
|
|
|
|
config HT_CHAIN_END_UNITID_BASE
|
|
hex
|
|
default 0x20
|
|
depends on BOARD_NVIDIA_L1_2PVV
|
|
|
|
config USE_INIT
|
|
bool
|
|
default n
|
|
depends on BOARD_NVIDIA_L1_2PVV
|
|
|
|
config SERIAL_CPU_INIT
|
|
bool
|
|
default n
|
|
depends on BOARD_NVIDIA_L1_2PVV
|
|
|
|
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
|
hex
|
|
default 0x1022
|
|
depends on BOARD_NVIDIA_L1_2PVV
|
|
|
|
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
|
hex
|
|
default 0x2b80
|
|
depends on BOARD_NVIDIA_L1_2PVV
|
|
|
|
config IRQ_SLOT_COUNT
|
|
int
|
|
default 11
|
|
depends on BOARD_NVIDIA_L1_2PVV
|