Files
system76-coreboot/src
Shaunak Saha b599919495 google/reef: Remove setting of GPIO_TIER1_SCI enable bit
This patch removes setting of gpio_tier1_sci_en from mainboard
smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl
now.

BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
     Also from S0iX system is resuming for WIFI wake.

Change-Id: I26fd3fd9fcc83c988bcff1bda4da7a2e3da98ce6
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16566
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-15 01:20:06 +02:00
..
2016-07-31 19:25:40 +02:00
2016-09-12 20:05:30 +02:00
2016-09-07 13:55:05 +02:00
2016-09-08 23:19:06 +02:00
2016-09-13 17:26:21 +02:00
2016-09-06 22:49:06 +02:00