b66757fc58
This patch adds following changes,
- APL, CFL, DENVERTON soc's using same implementation to setup and
teardown FSP CAR. Hence cache_as_ram_fsp.S from soc folder is
cosolidated into one file and moved to common code CPU car folder.
- exit_car_fsp.S is from APL, DNV soc folder is clubbed into one file
and moved to common CPU car.
- The new file apollolake/fspcar.c is addded to pass tempraminit
parameters.
- Coffee lake Soc uses FSPT to support Intel Security features like
BootGuard verify boot and Measured boot. Add FSP CAR support for CFL
by programming tempraminit parameters and add FSP_T_XIP default if
FSP_CAR is selected.
BUG= None
TEST= Build for both CFL RVP11 & RVP8 and verified for successful CAR setup.
Build for both leafhill and harcuvar platform by selecting CONFIG_FSP_CAR
without errors.
Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
277 lines
6.0 KiB
Plaintext
277 lines
6.0 KiB
Plaintext
config SOC_INTEL_CANNONLAKE
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bool
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help
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Intel Cannonlake support
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config SOC_INTEL_COFFEELAKE
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bool
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default n
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select SOC_INTEL_CANNONLAKE
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help
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Intel Coffeelake support
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config SOC_INTEL_CANNONLAKE_PCH_H
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bool
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default n
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help
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Choose this option if you have a PCH-H chipset.
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if SOC_INTEL_CANNONLAKE
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select ACPI_NHLT
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_RAMSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_VERSTAGE_X86_32
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select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
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select BOOT_DEVICE_SUPPORTS_WRITES
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select C_ENVIRONMENT_BOOTBLOCK
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select CACHE_MRC_SETTINGS
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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select COMMON_FADT
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select GENERIC_GPIO_LIB
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select HAVE_FSP_GOP
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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select HAVE_MONOTONIC_TIMER
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select HAVE_SMI_HANDLER
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select IDT_IN_EVERY_STAGE
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select INTEL_GMA_ACPI
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select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
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select IOAPIC
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select MRC_SETTINGS_PROTECT
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select PARALLEL_MP
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select PARALLEL_MP_AP_WORK
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select PLATFORM_USES_FSP2_0
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select POSTCAR_CONSOLE
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select POSTCAR_STAGE
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select REG_SCRIPT
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select SMM_TSEG
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select SMP
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select SOC_AHCI_PORT_IMPLEMENTED_INVERT
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select PMC_GLOBAL_RESET_ENABLE_LOCK
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_ACPI
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select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
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select SOC_INTEL_COMMON_BLOCK_CPU
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select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
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select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
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select SOC_INTEL_COMMON_BLOCK_HDA
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select SOC_INTEL_COMMON_BLOCK_SA
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select SOC_INTEL_COMMON_BLOCK_SMM
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select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
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select SOC_INTEL_COMMON_PCH_BASE
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select SOC_INTEL_COMMON_NHLT
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select SOC_INTEL_COMMON_RESET
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select SSE2
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select SUPPORT_CPU_UCODE_IN_CBFS
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select TSC_CONSTANT_RATE
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select TSC_MONOTONIC_TIMER
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select UDELAY_TSC
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select UDK_2017_BINDING
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select DISPLAY_FSP_VERSION_INFO
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select FSP_T_XIP if FSP_CAR
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config UART_DEBUG
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bool "Enable UART debug port."
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default n
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select CONSOLE_SERIAL
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select BOOTBLOCK_CONSOLE
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select DRIVERS_UART
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select DRIVERS_UART_8250MEM_32
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select NO_UART_ON_SUPERIO
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config UART_FOR_CONSOLE
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int "Index for LPSS UART port to use for console"
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default 2 if DRIVERS_UART_8250MEM_32
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default 0
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help
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Index for LPSS UART port to use for console:
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0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
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config DCACHE_RAM_BASE
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default 0xfef00000
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config DCACHE_RAM_SIZE
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default 0x40000
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage.
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x4000
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help
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The amount of anticipated stack usage in CAR by bootblock and
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other stages.
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config IFD_CHIPSET
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string
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default "cnl"
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config IED_REGION_SIZE
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hex
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default 0x400000
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config HEAP_SIZE
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hex
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default 0x8000
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config NHLT_DMIC_1CH_16B
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bool
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depends on ACPI_NHLT
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default n
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help
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Include DSP firmware settings for 1 channel 16B DMIC array.
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config NHLT_DMIC_2CH_16B
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bool
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depends on ACPI_NHLT
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default n
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help
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Include DSP firmware settings for 2 channel 16B DMIC array.
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config NHLT_DMIC_4CH_16B
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bool
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depends on ACPI_NHLT
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default n
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help
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Include DSP firmware settings for 4 channel 16B DMIC array.
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config NHLT_MAX98357
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bool
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depends on ACPI_NHLT
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default n
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help
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Include DSP firmware settings for headset codec.
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config NHLT_MAX98373
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bool
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depends on ACPI_NHLT
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default n
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help
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Include DSP firmware settings for headset codec.
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config NHLT_DA7219
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bool
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depends on ACPI_NHLT
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default n
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help
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Include DSP firmware settings for headset codec.
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config MAX_ROOT_PORTS
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int
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default 24 if SOC_INTEL_CANNONLAKE_PCH_H
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default 16
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config SMM_TSEG_SIZE
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hex
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default 0x800000
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config SMM_RESERVED_SIZE
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hex
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default 0x200000
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config PCR_BASE_ADDRESS
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hex
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default 0xfd000000
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help
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This option allows you to select MMIO Base Address of sideband bus.
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config CPU_BCLK_MHZ
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int
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default 100
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config SOC_INTEL_CANNONLAKE_MEMCFG_INIT
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bool
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default n
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config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
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int
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default 120
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config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
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int
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default 133
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config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
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int
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default 3
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config SOC_INTEL_I2C_DEV_MAX
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int
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default 4 if SOC_INTEL_CANNONLAKE_PCH_H
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default 6
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# Clock divider parameters for 115200 baud rate
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config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
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hex
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default 0x30
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config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
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hex
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default 0xc35
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config CHROMEOS
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select CHROMEOS_RAMOOPS_DYNAMIC
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config VBOOT
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select VBOOT_SEPARATE_VERSTAGE
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select VBOOT_OPROM_MATTERS
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select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
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select VBOOT_STARTS_IN_BOOTBLOCK
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select VBOOT_VBNV_CMOS
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select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
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config C_ENV_BOOTBLOCK_SIZE
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hex
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default 0x8000
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config CBFS_SIZE
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hex
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default 0x200000
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choice
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prompt "Cache-as-ram implementation"
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default USE_CANNONLAKE_CAR_NEM_ENHANCED if MAINBOARD_HAS_CHROMEOS
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default USE_CANNONLAKE_FSP_CAR
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help
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This option allows you to select how cache-as-ram (CAR) is set up.
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config USE_CANNONLAKE_CAR_NEM_ENHANCED
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bool "Enhanced Non-evict mode"
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select SOC_INTEL_COMMON_BLOCK_CAR
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select INTEL_CAR_NEM_ENHANCED
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help
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A current limitation of NEM (Non-Evict mode) is that code and data
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sizes are derived from the requirement to not write out any modified
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cache line. With NEM, if there is no physical memory behind the
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cached area, the modified data will be lost and NEM results will be
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inconsistent. ENHANCED NEM guarantees that modified data is always
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kept in cache while clean data is replaced.
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config USE_CANNONLAKE_FSP_CAR
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bool "Use FSP CAR"
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select FSP_CAR
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help
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Use FSP APIs to initialize and tear down the Cache-As-Ram.
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endchoice
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config FSP_HEADER_PATH
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string
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default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" if !SOC_INTEL_COFFEELAKE
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default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE
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config FSP_FD_PATH
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string
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depends on FSP_USE_REPO
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default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE
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endif
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