b887adf7a5
Change-Id: I0fd1a758d8838b3eea5640b41eee6a6893360aa3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
114 lines
2.4 KiB
C
114 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <device/mmio.h>
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#include <soc/intel/common/hda_verb.h>
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#include <soc/ramstage.h>
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#include <soc/igd.h>
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static const u32 minihd_verb_table[] = {
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/* coreboot specific header */
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0x80862808, // Codec Vendor / Device ID: Intel Broadwell Mini-HD
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0x80860101, // Subsystem ID
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0x00000004, // Number of jacks
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/* Enable 3rd Pin and Converter Widget */
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0x00878101,
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/* Pin Widget 5 - PORT B */
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0x00571C10,
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0x00571D00,
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0x00571E56,
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0x00571F18,
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/* Pin Widget 6 - PORT C */
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0x00671C20,
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0x00671D00,
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0x00671E56,
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0x00671F18,
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/* Pin Widget 7 - PORT D */
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0x00771C30,
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0x00771D00,
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0x00771E56,
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0x00771F18,
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/* Disable 3rd Pin and Converter Widget */
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0x00878100,
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/* Dummy entries to fill out the table */
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0x00878100,
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0x00878100,
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};
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static void minihd_init(struct device *dev)
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{
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struct resource *res;
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u8 *base;
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u32 reg32;
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int codec_mask, i;
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/* Find base address */
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (!res)
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return;
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base = res2mmio(res, 0, 0);
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printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base);
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/* Set Bus Master */
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pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
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/* Mini-HD configuration */
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reg32 = read32(base + 0x100c);
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reg32 &= 0xfffc0000;
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reg32 |= 0x4;
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write32(base + 0x100c, reg32);
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reg32 = read32(base + 0x1010);
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reg32 &= 0xfffc0000;
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reg32 |= 0x4b;
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write32(base + 0x1010, reg32);
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/* Init the codec and write the verb table */
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codec_mask = hda_codec_detect(base);
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if (codec_mask) {
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for (i = 3; i >= 0; i--) {
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if (codec_mask & (1 << i))
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hda_codec_init(base, i,
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sizeof(minihd_verb_table),
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minihd_verb_table);
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}
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}
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/* Set EM4/EM5 registers */
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write32(base + 0x0100c, igd_get_reg_em4());
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write32(base + 0x01010, igd_get_reg_em5());
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}
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static struct device_operations minihd_ops = {
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.read_resources = &pci_dev_read_resources,
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.set_resources = &pci_dev_set_resources,
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.enable_resources = &pci_dev_enable_resources,
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.init = &minihd_init,
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.ops_pci = &broadwell_pci_ops,
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};
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static const unsigned short pci_device_ids[] = {
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0x0a0c, /* Haswell */
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0x160c, /* Broadwell */
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0
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};
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static const struct pci_driver minihd_driver __pci_driver = {
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.ops = &minihd_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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