b8dc63bdfe
BUG=b:70232394 BRANCH=none TEST=emerge-reef coreboot emerge-glados Change-Id: Idb453a4d2411163e6b4a8422310bf272eac5d379 Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/22822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
54 lines
1.5 KiB
C
54 lines
1.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corporation..
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <drivers/i2c/designware/dw_i2c.h>
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#include <intelblocks/gspi.h>
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#include <soc/bootblock.h>
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asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
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{
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/* Call lib/bootblock.c main */
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bootblock_main_with_timestamp(base_timestamp);
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}
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void bootblock_soc_early_init(void)
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{
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bootblock_systemagent_early_init();
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bootblock_pch_early_init();
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bootblock_cpu_init();
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pch_early_iorange_init();
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if (IS_ENABLED(CONFIG_UART_DEBUG))
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pch_uart_init();
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}
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void bootblock_soc_init(void)
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{
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/* FSP 2.0 does not provide FSP-T/TempRamInit init support yet */
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if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1))
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bootblock_fsp_temp_ram_init();
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/*
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* Perform early chipset initialization before fsp memory init
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* example: pirq->irq programming, enabling smbus, set pmcbase
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* and abase, i2c programming and print platform info
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*/
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report_platform_info();
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pch_early_init();
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gspi_early_bar_init();
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}
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