b8df689a6a
Clone entirely from Icelake List of changes on top off initial icelake clone 1. Removed Descriptor Name for Memory mapped SPI flash and local APIC in northbridge.asl 2. Rearranged code in gpio.asl to move RBUF object under _CRS and made the file use ASL2.0 syntax. 3. Make use of absolute path for scs.asl 4. Remove unused smbus.asl 5. Rearranged code in nothbridge.asl to move MCRS object under _CRS, use absolute variable path and added TODO for further clean up. 6. Refer absolute variable path in scs.asl Change-Id: If967cb5904f543ce21eb6e89421df0e5673d2238 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
135 lines
2.5 KiB
Plaintext
135 lines
2.5 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/pcr_ids.h>
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Scope (\_SB.PCI0) {
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/*
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* Clear register 0x1C20/0x4820
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* Arg0 - PCR Port ID
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*/
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Method(SCSC, 1, Serialized)
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{
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PCRA (Arg0, 0x1C20, 0x0)
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PCRA (Arg0, 0x4820, 0x0)
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}
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/* EMMC */
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Device(PEMC) {
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Name(_ADR, 0x001A0000)
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Name (_DDN, "eMMC Controller")
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Name (TEMP, 0)
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OperationRegion(SCSR, PCI_Config, 0x00, 0x100)
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Field(SCSR, WordAcc, NoLock, Preserve) {
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Offset (0x84), /* PMECTRLSTATUS */
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PMCR, 16,
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Offset (0xA2), /* PG_CONFIG */
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, 2,
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PGEN, 1, /* PG_ENABLE */
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}
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Method(_INI) {
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/* Clear register 0x1C20/0x4820 */
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SCSC (PID_EMMC)
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}
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Method(_PS0, 0, Serialized) {
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Stall (50) // Sleep 50 us
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Store(0, PGEN) // Disable PG
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/* Clear register 0x1C20/0x4820 */
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SCSC (PID_EMMC)
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/* Set Power State to D0 */
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And (PMCR, 0xFFFC, PMCR)
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Store (PMCR, TEMP)
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}
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Method(_PS3, 0, Serialized) {
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Store(1, PGEN) // Enable PG
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/* Set Power State to D3 */
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Or (PMCR, 0x0003, PMCR)
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Store (PMCR, TEMP)
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}
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Device (CARD)
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{
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Name (_ADR, 0x00000008)
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Method (_RMV, 0, NotSerialized)
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{
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Return (0)
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}
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}
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}
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/* SD CARD */
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Device (SDXC)
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{
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Name (_ADR, 0x00140005)
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Name (_DDN, "SD Controller")
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Name (TEMP, 0)
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OperationRegion (SDPC, PCI_Config, 0x00, 0x100)
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Field (SDPC, WordAcc, NoLock, Preserve)
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{
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Offset (0x84), /* PMECTRLSTATUS */
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PMCR, 16,
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Offset (0xA2), /* PG_CONFIG */
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, 2,
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PGEN, 1, /* PG_ENABLE */
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}
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Method(_INI)
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{
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/* Clear register 0x1C20/0x4820 */
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SCSC (PID_SDX)
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}
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Method (_PS0, 0, Serialized)
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{
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Store (0, PGEN) /* Disable PG */
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/* Clear register 0x1C20/0x4820 */
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SCSC (PID_SDX)
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/* Set Power State to D0 */
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And (PMCR, 0xFFFC, PMCR)
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Store (PMCR, TEMP)
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}
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Method (_PS3, 0, Serialized)
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{
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Store (1, PGEN) /* Enable PG */
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/* Set Power State to D3 */
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Or (PMCR, 0x0003, PMCR)
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Store (PMCR, TEMP)
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}
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Device (CARD)
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{
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Name (_ADR, 0x00000008)
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Method (_RMV, 0, NotSerialized)
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{
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Return (1)
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}
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}
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} /* Device (SDXC) */
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}
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