b8e2027be8
to build, but by default all the tables that are available are built. Make PIRQ table build for qemu. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
129 lines
4.2 KiB
Plaintext
129 lines
4.2 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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## CONFIG_XIP_ROM_SIZE must be a power of 2.
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default CONFIG_XIP_ROM_SIZE = 64 * 1024
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include /config/nofailovercalculation.lb
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arch i386 end
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driver mainboard.o
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if CONFIG_GENERATE_PIRQ_TABLE
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object irq_tables.o
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end
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makerule ./failover.E
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depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
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action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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makerule ./failover.inc
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depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
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action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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makerule ./auto.E
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# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
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depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
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action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
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depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
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action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
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end
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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mainboardinit arch/i386/lib/cpu_reset.inc
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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if CONFIG_USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit cpu/amd/model_gx1/cpu_setup.inc
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mainboardinit cpu/amd/model_gx1/gx_setup.inc
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mainboardinit ./auto.inc
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dir /pc80
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config chip.h
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chip northbridge/amd/gx1 # Northbridge
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device pci_domain 0 on # PCI domain
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device pci 0.0 on end # Host bridge
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chip southbridge/amd/cs5530 # Southbridge
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device pci 0f.0 on end # Ethernet
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device pci 12.0 on # ISA bridge
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chip superio/nsc/pc87351 # Super I/O
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 on # COM2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.e on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.4 on # System wake-up control (SWC)
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irq 0x60 = 0x500
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end
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device pnp 2e.5 on # PS/2 mouse
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irq 0x70 = 12
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end
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device pnp 2e.6 on # PS/2 keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 2e.7 on # GPIO
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irq 0x60 = 0x800
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end
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device pnp 2e.8 on # Fan speed control
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irq 0x60 = 0x900
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end
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end
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end
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device pci 12.1 off end # SMI
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device pci 12.2 on end # IDE
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device pci 12.3 on end # Audio
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device pci 12.4 on end # VGA
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device pci 13.0 on end # USB
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register "ide0_enable" = "1"
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register "ide1_enable" = "0" # No connector on this board
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end
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end
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chip cpu/amd/model_gx1 # CPU
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end
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end
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