b95ef282ff
Identify PCH type by LPC device ID. This allows to identify the PCH without including northbridge headers. Tested: Lenovo X220 still boots. Change-Id: Ic3e15c1d8d4b1d1012d6204cc65de92d91431fbe Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
141 lines
2.9 KiB
C
141 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#define __SIMPLE_DEVICE__
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#include <console/console.h>
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#include <delay.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <stdint.h>
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#include "pch.h"
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int pch_silicon_revision(void)
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{
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static int pch_revision_id = -1;
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if (pch_revision_id < 0)
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pch_revision_id = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID);
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return pch_revision_id;
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}
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int pch_silicon_type(void)
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{
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static int pch_type = -1;
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if (pch_type < 0)
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pch_type = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1);
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return pch_type;
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}
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bool pch_is_mobile(void)
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{
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const u16 devids[] = {
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PCI_DID_INTEL_6_SERIES_MOBILE_SFF, PCI_DID_INTEL_6_SERIES_MOBILE,
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PCI_DID_INTEL_6_SERIES_UM67, PCI_DID_INTEL_6_SERIES_HM65,
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PCI_DID_INTEL_6_SERIES_HM67, PCI_DID_INTEL_6_SERIES_QS67,
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PCI_DID_INTEL_6_SERIES_QM67,
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PCI_DID_INTEL_7_SERIES_MOBILE, PCI_DID_INTEL_7_SERIES_MOBILE_SFF,
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PCI_DID_INTEL_7_SERIES_QM77, PCI_DID_INTEL_7_SERIES_QS77,
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PCI_DID_INTEL_7_SERIES_HM77, PCI_DID_INTEL_7_SERIES_UM77,
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PCI_DID_INTEL_7_SERIES_HM76, PCI_DID_INTEL_7_SERIES_HM75,
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PCI_DID_INTEL_7_SERIES_HM70, PCI_DID_INTEL_7_SERIES_NM70
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};
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u16 devid = pci_s_read_config16(PCH_LPC_DEV, PCI_DEVICE_ID);
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for (size_t i = 0; i < ARRAY_SIZE(devids); i++)
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if (devid == devids[i])
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return true;
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return false;
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}
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int pch_silicon_supported(int type, int rev)
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{
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int cur_type = pch_silicon_type();
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int cur_rev = pch_silicon_revision();
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switch (type) {
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case PCH_TYPE_CPT:
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/* CougarPoint minimum revision */
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if (cur_type == PCH_TYPE_CPT && cur_rev >= rev)
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return 1;
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/* PantherPoint any revision */
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if (cur_type == PCH_TYPE_PPT)
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return 1;
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break;
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case PCH_TYPE_PPT:
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/* PantherPoint minimum revision */
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if (cur_type == PCH_TYPE_PPT && cur_rev >= rev)
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return 1;
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break;
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}
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return 0;
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}
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#define IOBP_RETRY 1000
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static inline int iobp_poll(void)
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{
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unsigned int try = IOBP_RETRY;
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u32 data;
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while (try--) {
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data = RCBA32(IOBPS);
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if ((data & 1) == 0)
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return 1;
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udelay(10);
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}
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printk(BIOS_ERR, "IOBP timeout\n");
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return 0;
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}
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void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
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{
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u32 data;
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/* Set the address */
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RCBA32(IOBPIRI) = address;
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/* READ OPCODE */
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if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
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RCBA32(IOBPS) = IOBPS_RW_BX;
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else
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RCBA32(IOBPS) = IOBPS_READ_AX;
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if (!iobp_poll())
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return;
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/* Read IOBP data */
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data = RCBA32(IOBPD);
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if (!iobp_poll())
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return;
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/* Check for successful transaction */
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if ((RCBA32(IOBPS) & 0x6) != 0) {
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printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address);
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return;
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}
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/* Update the data */
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data &= andvalue;
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data |= orvalue;
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/* WRITE OPCODE */
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if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
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RCBA32(IOBPS) = IOBPS_RW_BX;
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else
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RCBA32(IOBPS) = IOBPS_WRITE_AX;
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if (!iobp_poll())
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return;
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/* Write IOBP data */
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RCBA32(IOBPD) = data;
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if (!iobp_poll())
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return;
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}
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