b995f436b3
We don't need to do explicit pci_io_read/write operations, as we can use MMCONF everywhere. AGESA code still enables extended cf8/cfc should it be required by payload or OS. Change-Id: I278e5e26eb9a247f67927cbc67e04f081ca50f7b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17535 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
41 lines
926 B
Plaintext
41 lines
926 B
Plaintext
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2012 Advanced Micro Devices, Inc.
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# Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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config CPU_AMD_AGESA_FAMILY15_RL
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bool
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select MMCONF_SUPPORT_DEFAULT
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select X86_AMD_FIXED_MTRRS
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if CPU_AMD_AGESA_FAMILY15_RL
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config CPU_ADDR_BITS
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int
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default 48
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config CBB
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hex
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default 0x0
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config CDB
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hex
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default 0x18
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config XIP_ROM_SIZE
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hex
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default 0x100000
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endif # CPU_AMD_AGESA_FAMILY15_RL
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