b9c049a368
This effectively means it is possible to run another bootblock located at top_of_flash - 64K. The i82801gx southbridge has the ability to swap the two top 64K ranges by flipping the BUC.TS bit (RCBA[3414] bit0). This allows coreboot to build roms with a bootblock at the top swap offset by selecting CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK. Change-Id: Id96e10aea3e5fd955d45287134eb8643be414de9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
53 lines
1.3 KiB
Plaintext
53 lines
1.3 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008-2009 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config SOUTHBRIDGE_INTEL_I82801GX
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bool
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select SOUTHBRIDGE_INTEL_COMMON
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select IOAPIC
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select HAVE_HARD_RESET
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select HAVE_USBDEBUG
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select USE_WATCHDOG_ON_BOOT
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select HAVE_SMI_HANDLER
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select COMMON_FADT
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select SOUTHBRIDGE_INTEL_COMMON_GPIO
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select SOUTHBRIDGE_INTEL_COMMON_SMBUS
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select SOUTHBRIDGE_INTEL_COMMON_SPI
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select HAVE_INTEL_CHIPSET_LOCKDOWN
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select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
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select INTEL_HAS_TOP_SWAP
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if SOUTHBRIDGE_INTEL_I82801GX
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config EHCI_BAR
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hex
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default 0xfef00000
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "southbridge/intel/i82801gx/bootblock.c"
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config HPET_MIN_TICKS
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hex
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default 0x80
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config INTEL_TOP_SWAP_BOOTBLOCK_SIZE
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hex
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# Always 64K, all other options are invalid
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default 0x10000
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endif
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