b9e6e1ab35
This moves the prototype for power_enable_hw_thermal_trip() to a generic location so it can be used by generalized thermal management code. The implementation will still be CPU-specific. Change-Id: Iae449cb8c72c8441dedaf65b73db9898b4730cef Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3105 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
87 lines
2.5 KiB
C
87 lines
2.5 KiB
C
/*
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* (C) Copyright 2012 Samsung Electronics
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* Register map for Exynos5 PMU
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __EXYNOS5_POWER_H__
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#define __EXYNOS5_POWER_H__
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#define MIPI_PHY1_CONTROL_ENABLE (1 << 0)
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#define MIPI_PHY1_CONTROL_M_RESETN (1 << 2)
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#define POWER_USB_HOST_PHY_CTRL_EN (1 << 0)
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#define POWER_PS_HOLD_CONTROL_DATA_HIGH (1 << 8)
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#define POWER_ENABLE_HW_TRIP (1UL << 31)
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#define DPTX_PHY_ENABLE (1 << 0)
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/* PMU_DEBUG bits [12:8] = 0x1000 selects XXTI clock source */
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#define PMU_DEBUG_XXTI 0x1000
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/* Mask bit[12:8] for xxti clock selection */
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#define PMU_DEBUG_CLKOUT_SEL_MASK 0x1f00
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/* Power Management Unit register map */
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struct exynos5_power {
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/* Add registers as and when required */
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uint8_t reserved1[0x0400];
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uint32_t sw_reset; /* 0x0400 */
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uint8_t reserved2[0x0304];
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uint32_t usb_host_phy_ctrl; /* 0x0708 */
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uint8_t reserved3[0x8];
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uint32_t mipi_phy1_control; /* 0x0714 */
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uint8_t reserved4[0x8];
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uint32_t dptx_phy_control; /* 0x0720 */
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uint8_t reserved5[0xdc];
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uint32_t inform0; /* 0x0800 */
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uint32_t inform1; /* 0x0804 */
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uint8_t reserved6[0x1f8];
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uint32_t pmu_debug; /* 0x0A00*/
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uint8_t reserved7[0x2908];
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uint32_t ps_hold_ctrl; /* 0x330c */
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} __attribute__ ((__packed__));
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/**
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* Perform a software reset.
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*/
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void power_reset(void);
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/**
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* Power off the system; it should never return.
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*/
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void power_shutdown(void);
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/* Enable DPTX PHY */
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void power_enable_dp_phy(void);
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void power_enable_usb_phy(void);
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void power_disable_usb_phy(void);
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/* Initialize the pmic voltages to power up the system */
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int power_init(void);
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/* Read the reset status. */
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uint32_t power_read_reset_status(void);
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/* Read the resume function and call it. */
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void power_exit_wakeup(void);
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/* pmu debug is used for xclkout, enable xclkout with source as XXTI */
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void power_enable_xclkout(void);
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#endif
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