ba28e8d73b
Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16291 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
72 lines
2.0 KiB
C
72 lines
2.0 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <device/pci_ids.h>
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#include <arch/io.h> /* inl, outl */
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#include "SBPLATFORM.h"
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#include "sb_cimx.h"
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#include "cfg.h" /*sb800_cimx_config*/
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#include "cbmem.h"
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/**
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* @brief Get SouthBridge device number
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* @param[in] bus target bus number
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* @return southbridge device number
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*/
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u32 get_sbdn(u32 bus)
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{
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device_t dev;
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printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__);
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//dev = PCI_DEV(bus, 0x14, 0);
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dev = pci_locate_device_on_bus(
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PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_SM),
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bus);
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printk(BIOS_DEBUG, "SB800 - %s - %s - End.\n", __FILE__, __func__);
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return (dev >> 15) & 0x1f;
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}
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/**
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* @brief South Bridge CIMx romstage entry,
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* wrapper of sbPowerOnInit entry point.
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*/
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void sb_Poweron_Init(void)
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{
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AMDSBCFG sb_early_cfg;
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sb800_cimx_config(&sb_early_cfg);
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//sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
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//AmdSbDispatcher(&sb_early_cfg);
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//TODO
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//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
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// VerifyImage() will fail, LocateImage() takes minutes to find the image.
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sbPowerOnInit(&sb_early_cfg);
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}
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/**
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* CIMX not set the clock to 48Mhz until sbBeforePciInit,
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* coreboot may need to set this even more earlier
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*/
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void sb800_clk_output_48Mhz(void)
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{
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/* AcpiMMioDecodeEn */
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RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0 + BIT1), BIT0);
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*(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
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*(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */
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}
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