ba28e8d73b
Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16291 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
144 lines
3.9 KiB
C
144 lines
3.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2005 AMD
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* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pnp.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <pc80/mc146818rtc.h>
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#include <pc80/isa-dma.h>
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#include <arch/io.h>
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#include <arch/ioapic.h>
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#include "bcm5785.h"
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static void lpc_init(device_t dev)
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{
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/* Initialize the real time clock */
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cmos_init(0);
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/* Initialize isa dma */
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isa_dma_init();
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}
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static void bcm5785_lpc_read_resources(device_t dev)
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{
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struct resource *res;
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/* Get the normal pci resources of this device */
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pci_dev_read_resources(dev);
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/* Add an extra subtractive resource for both memory and I/O. */
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
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res->base = 0;
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res->size = 0x1000;
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res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
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res->base = 0xff800000;
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res->size = 0x00800000; /* 8 MB for flash */
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res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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res = new_resource(dev, 3); /* IOAPIC */
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res->base = IO_APIC_ADDR;
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res->size = 0x00001000;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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}
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/**
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* Enable resources for children devices.
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*
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* @param dev The device whos children's resources are to be enabled.
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*/
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static void bcm5785_lpc_enable_childrens_resources(device_t dev)
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{
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struct bus *link;
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uint32_t reg;
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reg = pci_read_config8(dev, 0x44);
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for (link = dev->link_list; link; link = link->next) {
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device_t child;
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for (child = link->children; child; child = child->sibling) {
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if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
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struct resource *res;
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for (res = child->resource_list; res; res = res->next) {
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unsigned long base, end; // don't need long long
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if (!(res->flags & IORESOURCE_IO)) continue;
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base = res->base;
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end = resource_end(res);
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printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
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switch(base) {
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case 0x60: //KBC
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case 0x64:
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reg |= (1<<29);
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case 0x3f8: // COM1
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reg |= (1<<6); break;
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case 0x2f8: // COM2
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reg |= (1<<7); break;
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case 0x378: // Parallal 1
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reg |= (1<<0); break;
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case 0x3f0: // FD0
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reg |= (1<<26); break;
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case 0x220: // Aduio 0
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reg |= (1<<14); break;
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case 0x300: // Midi 0
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reg |= (1<<18); break;
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}
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}
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}
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}
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}
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pci_write_config32(dev, 0x44, reg);
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}
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static void bcm5785_lpc_enable_resources(device_t dev)
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{
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pci_dev_enable_resources(dev);
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bcm5785_lpc_enable_childrens_resources(dev);
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}
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static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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{
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pci_write_config32(dev, 0x40,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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static struct pci_operations lops_pci = {
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.set_subsystem = lpci_set_subsystem,
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};
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static struct device_operations lpc_ops = {
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.read_resources = bcm5785_lpc_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = bcm5785_lpc_enable_resources,
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.init = lpc_init,
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.scan_bus = scan_lpc_bus,
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// .enable = bcm5785_enable,
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.ops_pci = &lops_pci,
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};
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static const struct pci_driver lpc_driver __pci_driver = {
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.ops = &lpc_ops,
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.vendor = PCI_VENDOR_ID_SERVERWORKS,
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.device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_LPC,
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};
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