ba28e8d73b
Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16291 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
185 lines
4.3 KiB
C
185 lines
4.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Tyan Computer
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* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
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* Copyright (C) 2006,2007 AMD
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* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
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* Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
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* Written by Morgan Tsai <my_tsai@sis.com> for SiS.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <arch/io.h>
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#include "sis966.h"
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#include "chip.h"
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uint8_t SiS_SiS5513_init[49][3]={
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{0x04, 0xFF, 0x05},
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{0x0D, 0xFF, 0x80},
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{0x2C, 0xFF, 0x39},
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{0x2D, 0xFF, 0x10},
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{0x2E, 0xFF, 0x13},
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{0x2F, 0xFF, 0x55},
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{0x50, 0xFF, 0xA2},
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{0x51, 0xFF, 0x21},
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{0x53, 0xFF, 0x21},
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{0x54, 0xFF, 0x2A},
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{0x55, 0xFF, 0x96},
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{0x52, 0xFF, 0xA2},
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{0x56, 0xFF, 0x81},
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{0x57, 0xFF, 0xC0},
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{0x60, 0xFF, 0xFB},
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{0x61, 0xFF, 0xAA},
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{0x62, 0xFF, 0xFB},
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{0x63, 0xFF, 0xAA},
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{0x81, 0xFF, 0xB3},
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{0x82, 0xFF, 0x72},
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{0x83, 0xFF, 0x40},
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{0x85, 0xFF, 0xB3},
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{0x86, 0xFF, 0x72},
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{0x87, 0xFF, 0x40},
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{0x94, 0xFF, 0xC0},
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{0x95, 0xFF, 0x08},
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{0x96, 0xFF, 0xC0},
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{0x97, 0xFF, 0x08},
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{0x98, 0xFF, 0xCC},
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{0x99, 0xFF, 0x04},
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{0x9A, 0xFF, 0x0C},
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{0x9B, 0xFF, 0x14},
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{0xA0, 0xFF, 0x11},
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{0x57, 0xFF, 0xD0},
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{0xD8, 0xFE, 0x01}, // Com reset
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{0xC8, 0xFE, 0x01},
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{0xC4, 0xFF, 0xFF}, // Clear status
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{0xC5, 0xFF, 0xFF},
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{0xC6, 0xFF, 0xFF},
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{0xC7, 0xFF, 0xFF},
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{0xD4, 0xFF, 0xFF},
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{0xD5, 0xFF, 0xFF},
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{0xD6, 0xFF, 0xFF},
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{0xD7, 0xFF, 0xFF},
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{0x2C, 0xFF, 0x39}, // set subsystem ID
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{0x2D, 0xFF, 0x10},
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{0x2E, 0xFF, 0x13},
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{0x2F, 0xFF, 0x55},
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{0x00, 0x00, 0x00} //End of table
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};
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static void ide_init(struct device *dev)
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{
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struct southbridge_sis_sis966_config *conf;
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/* Enable ide devices so the linux ide driver will work */
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uint32_t dword;
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uint16_t word;
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uint8_t byte;
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conf = dev->chip_info;
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printk(BIOS_DEBUG, "IDE_INIT:---------->\n");
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//-------------- enable IDE (SiS5513) -------------------------
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{
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uint8_t temp8;
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int i=0;
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while (SiS_SiS5513_init[i][0] != 0) {
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temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]);
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temp8 &= SiS_SiS5513_init[i][1];
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temp8 |= SiS_SiS5513_init[i][2];
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pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8);
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i++;
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};
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}
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//-----------------------------------------------------------
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word = pci_read_config16(dev, 0x50);
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/* Ensure prefetch is disabled */
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word &= ~((1 << 15) | (1 << 13));
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if (conf->ide1_enable) {
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/* Enable secondary ide interface */
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word |= (1<<0);
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printk(BIOS_DEBUG, "IDE1\t");
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}
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if (conf->ide0_enable) {
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/* Enable primary ide interface */
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word |= (1<<1);
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printk(BIOS_DEBUG, "IDE0\n");
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}
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word |= (1<<12);
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word |= (1<<14);
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pci_write_config16(dev, 0x50, word);
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byte = 0x20 ; // Latency: 64-->32
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pci_write_config8(dev, 0xd, byte);
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dword = pci_read_config32(dev, 0xf8);
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dword |= 12;
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pci_write_config32(dev, 0xf8, dword);
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#if DEBUG_IDE
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{
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int i;
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printk(BIOS_DEBUG, "****** IDE PCI config ******");
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printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
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for (i=0;i<0xff;i+=4) {
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if ((i%16)==0)
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printk(BIOS_DEBUG, "\n%02x: ", i);
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printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
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}
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printk(BIOS_DEBUG, "\n");
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}
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#endif
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printk(BIOS_DEBUG, "IDE_INIT:<----------\n");
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}
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static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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{
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pci_write_config32(dev, 0x40,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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static struct pci_operations lops_pci = {
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.set_subsystem = lpci_set_subsystem,
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};
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static struct device_operations ide_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = ide_init,
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.scan_bus = 0,
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// .enable = sis966_enable,
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.ops_pci = &lops_pci,
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};
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static const struct pci_driver ide_driver __pci_driver = {
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.ops = &ide_ops,
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.vendor = PCI_VENDOR_ID_SIS,
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.device = PCI_DEVICE_ID_SIS_SIS966_IDE,
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};
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