Marshall Dawson ba8751fc72 soc/amd/stoneyridge: Rearrange southbridge.h more ...

Move the SPI base address register definition to D14F3.  This was
missed in:
  bba043 amd/stoneyridge: Rearrange southbridge.h

Change-Id: Ia722339418c118bdf4b000bbf97ae4266e9b3be2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

2018-10-14 19:11:34 +00:00

..

acpi

arch/x86: Add common AMD ACPI hardware definitions

2017-11-10 19:15:38 +00:00

arch

libpayload: arm64: Conform to new coreboot lib_helpers.h and assume EL2

2018-10-12 20:14:54 +00:00

commonlib

commonlib/storage: Make pci sdhci code compile in romstage

2018-10-11 10:57:07 +00:00

console

Move compiler.h to commonlib

2018-10-08 16:57:27 +00:00

cpu

src: Move common IA-32 MSRs to <cpu/x86/msr.h>

2018-10-11 21:06:53 +00:00

device

Move compiler.h to commonlib

2018-10-08 16:57:27 +00:00

drivers

drivers/intel/fsp2_0: Hook up IntelFSP repo

2018-10-12 23:20:53 +00:00

ec

ec/google/chromeec: Add support for querying ec board id in smm stage

2018-10-11 23:58:10 +00:00

include

src: Move common IA-32 MSRs to <cpu/x86/msr.h>

2018-10-11 21:06:53 +00:00

lib

selfboot: remove bounce buffers

2018-10-11 17:42:41 +00:00

mainboard

amd/stoneyridge: Rename GppClkCntrl fields

2018-10-12 15:16:23 +00:00

northbridge

src: Move common IA-32 MSRs to <cpu/x86/msr.h>

2018-10-11 21:06:53 +00:00

security

Move compiler.h to commonlib

2018-10-08 16:57:27 +00:00

soc

soc/amd/stoneyridge: Rearrange southbridge.h more

2018-10-14 19:11:34 +00:00

southbridge

Move compiler.h to commonlib

2018-10-08 16:57:27 +00:00

superio

superio/ite/it8721f: Add SuperIO ACPI declarations

2018-08-21 14:45:36 +00:00

vendorcode

drivers/intel/fsp2_0: Hook up IntelFSP repo

2018-10-12 23:20:53 +00:00

Kconfig

src/Kconfig: Drop a superfluous word

2018-10-01 15:28:47 +00:00