baf27dbaeb
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with. Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
35 lines
877 B
Plaintext
35 lines
877 B
Plaintext
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <memlayout.h>
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#include <arch/header.ld>
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/*
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* Note: The BootROM loads the 8K BL1 at [0x2020000:0x2022000), so the bootblock
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* must be placed after that. After the handoff, the space can be reclaimed.
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*/
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SECTIONS
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{
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SRAM_START(0x2020000)
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/* 17K hole, includes BL1 */
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/* Bootblock is preceded by 16 byte variable length BL2 checksum. */
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BOOTBLOCK(0x2024410, 32K - 16)
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/* 15K hole */
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ROMSTAGE(0x2030000, 128K)
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/* 32K hole */
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TTB(0x2058000, 16K)
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PRERAM_CBFS_CACHE(0x205C000, 66K)
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CBFS_MCACHE(0x206C800, 8K)
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FMAP_CACHE(0x206E800, 2K)
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STACK(0x206F000, 16K)
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/* 1K hole for weird kernel-shared CPU/SMP state structure that doesn't
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* seem to be implemented right now? */
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SRAM_END(0x2074000)
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DRAM_START(0x20000000)
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RAMSTAGE(0x20000000, 128K)
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POSTRAM_CBFS_CACHE(0x21000000, 8M)
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DMA_COHERENT(0x77300000, 1M)
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}
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