bbba201165
Change-Id: Idca56583c1c8dc41ad11d915ec3e8be781fb4e48 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
94 lines
2.1 KiB
C
94 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <assert.h>
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <stage_cache.h>
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#include <types.h>
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#include <inttypes.h>
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/*
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* Subregions within SMM
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* +-------------------------+
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* | IED | IED_REGION_SIZE
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* +-------------------------+
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* | External Stage Cache | SMM_RESERVED_SIZE
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* +-------------------------+
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* | code and data |
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* | (TSEG) |
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* +-------------------------+ TSEG
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*/
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int smm_subregion(int sub, uintptr_t *start, size_t *size)
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{
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uintptr_t sub_base;
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size_t sub_size;
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const size_t ied_size = CONFIG_IED_REGION_SIZE;
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const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
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if (CONFIG(SMM_TSEG))
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smm_region(&sub_base, &sub_size);
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else if (CONFIG(SMM_ASEG))
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aseg_region(&sub_base, &sub_size);
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else
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return -1;
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ASSERT(IS_ALIGNED(sub_base, sub_size));
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ASSERT(sub_size > (cache_size + ied_size));
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switch (sub) {
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case SMM_SUBREGION_HANDLER:
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/* Handler starts at the base of TSEG. */
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sub_size -= ied_size;
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sub_size -= cache_size;
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break;
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case SMM_SUBREGION_CACHE:
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/* External cache is in the middle of TSEG. */
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sub_base += sub_size - (ied_size + cache_size);
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sub_size = cache_size;
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break;
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case SMM_SUBREGION_CHIPSET:
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/* IED is at the top. */
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sub_base += sub_size - ied_size;
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sub_size = ied_size;
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break;
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default:
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*start = 0;
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*size = 0;
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return -1;
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}
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*start = sub_base;
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*size = sub_size;
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return 0;
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}
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void stage_cache_external_region(void **base, size_t *size)
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{
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if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) {
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printk(BIOS_ERR, "No cache SMM subregion.\n");
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*base = NULL;
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*size = 0;
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}
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}
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void smm_list_regions(void)
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{
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uintptr_t base;
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size_t size;
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int i;
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smm_region(&base, &size);
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if (!size)
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return;
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printk(BIOS_DEBUG, "SMM Memory Map\n");
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printk(BIOS_DEBUG, "SMRAM : 0x%" PRIxPTR " 0x%zx\n", base, size);
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for (i = 0; i < SMM_SUBREGION_NUM; i++) {
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if (smm_subregion(i, &base, &size))
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continue;
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printk(BIOS_DEBUG, " Subregion %d: 0x%" PRIxPTR " 0x%zx\n", i, base, size);
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}
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}
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