bbf0a418c4
Set open-drain GPIOs for ChromeOS as input and bias-disable mode. After applying this patch, the voltage of these pins will become the expected value 1.8V (previously 1.0V), preventing wrong judgement of low/high. Reference document: MT8188G_GPIO_Formal_Application_Spec_V0.3 BUG=b:274058085 TEST=build pass Change-Id: I057716df6c59efb84fc395109db022b82ce528c4 Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73963 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
49 lines
1.5 KiB
C
49 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __MAINBOARD_GOOGLE_GERALT_GPIO_H__
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#define __MAINBOARD_GOOGLE_GERALT_GPIO_H__
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#include <soc/gpio.h>
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#define GPIO_AP_DISP_BKLTEN GPIO(GPIO01)
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#define GPIO_AP_EC_WARM_RST_REQ GPIO(DPI_HSYNC)
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#define GPIO_AP_WP_ODL GPIO(GPIO15)
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#define GPIO_BEEP_ON_OD GPIO(KPROW0)
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#define GPIO_EC_AP_INT_ODL GPIO(DPI_DE)
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#define GPIO_EC_AP_HPD_OD GPIO(DPTX_HPD)
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#define GPIO_EC_AP_HID_INT_ODL GPIO(DPI_VSYNC)
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#define GPIO_EC_AP_RSVD0_ODL GPIO(MSDC2_DAT1)
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#define GPIO_EN_SPKR GPIO(I2SIN_D1)
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#define GPIO_GSC_AP_INT_ODL GPIO(GPIO00)
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#define GPIO_RST_SPKR_L GPIO(I2SO2_D1)
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#define GPIO_XHCI_INIT_DONE GPIO(DPI_CK)
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#define GPIO_SAR_INT_ODL GPIO(USB1_VBUS_VALID)
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#define GPIO_HP_INT_ODL GPIO(I2SIN_BCK)
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#define GPIO_SPKR_INT_ODL GPIO(I2SIN_WS)
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#define GPIO_I2SI1_LRCK GPIO(I2SO2_D2)
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#define GPIO_I2SI1_BCK GPIO(I2SIN_D3)
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#define GPIO_I2SO1_D0 GPIO(GPIO11)
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#define GPIO_PCIE_WAKE_1V8_ODL GPIO(PCIE_WAKE_N)
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#define GPIO_PCIE_CLKREQ_1V8_ODL GPIO(PCIE_CLKREQ_N)
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#define GPIO_TCHSCR_INT_1V8_L GPIO(DPI_D12)
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#define GPIO_MT7921_PMU_EN_1V8 GPIO(DPI_D14)
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#define GPIO_EDP_BL_PWM_1V8 GPIO(DISP_PWM1)
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#define GPIO_EDP_HPD_1V8 GPIO(GPIO17)
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#define GPIO_EN_PP3300_EDP_DISP_X GPIO(DSI1_LCM_RST)
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#define GPIO_DISP_RST_1V8_L GPIO(DSI0_LCM_RST)
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#define GPIO_EN_PPVAR_MIPI_DISP GPIO(GPIO03)
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#define GPIO_EN_PPVAR_MIPI_DISP_150MA GPIO(GPIO04)
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#define GPIO_MIPI_BL_PWM_1V8 GPIO(DISP_PWM0)
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#define GPIO_SD_CD_ODL GPIO(I2SIN_MCK)
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#define GPIO_USB3_HUB_RST_L GPIO(MSDC2_DAT0)
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void setup_chromeos_gpios(void);
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#endif
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