0aada3cddb
There's no need to have the bootblock in its own sub-directory, so move it to each SoC's main directory to avoid clutter. This makes soc/amd more consistent with the coreboot code base in src/northbridge, src/southbridge and src/soc with the exception of src/soc/intel. Change-Id: I78a9ce1cd0d790250a66c82bb1d8aa6c3b4f7162 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47982 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
105 lines
3.0 KiB
C
105 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <stdint.h>
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#include <assert.h>
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <smp/node.h>
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#include <bootblock_common.h>
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#include <amdblocks/agesawrapper.h>
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#include <amdblocks/agesawrapper_call.h>
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#include <amdblocks/amd_pci_mmconf.h>
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#include <amdblocks/biosram.h>
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#include <soc/pci_devs.h>
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#include <soc/cpu.h>
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#include <soc/southbridge.h>
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#include <amdblocks/psp.h>
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#include <timestamp.h>
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#include <halt.h>
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#if CONFIG_PI_AGESA_TEMP_RAM_BASE < 0x100000
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#error "Error: CONFIG_PI_AGESA_TEMP_RAM_BASE must be >= 1MB"
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#endif
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#if CONFIG_PI_AGESA_CAR_HEAP_BASE < 0x100000
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#error "Error: CONFIG_PI_AGESA_CAR_HEAP_BASE must be >= 1MB"
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#endif
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/* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */
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static void amd_initmmio(void)
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{
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msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
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int mtrr;
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/*
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* todo: AGESA currently writes variable MTRRs. Once that is
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* corrected, un-hardcode this MTRR.
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*
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* Be careful not to use get_free_var_mtrr/set_var_mtrr pairs
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* where all cores execute the path. Both cores within a compute
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* unit share MTRRs. Programming core0 has the appearance of
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* modifying core1 too. Using the pair again will create
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* duplicate copies.
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*/
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mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_FLASH;
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set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
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mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_CAR_HEAP;
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set_var_mtrr(mtrr, CONFIG_PI_AGESA_CAR_HEAP_BASE,
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CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_WRBACK);
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mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_TEMPRAM;
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set_var_mtrr(mtrr, CONFIG_PI_AGESA_TEMP_RAM_BASE,
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CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_UNCACHEABLE);
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}
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asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
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{
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enable_pci_mmconf();
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amd_initmmio();
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/*
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* Call lib/bootblock.c main with BSP, shortcut for APs
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*/
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if (!boot_cpu()) {
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void (*ap_romstage_entry)(void) =
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(void (*)(void))get_ap_entry_ptr();
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ap_romstage_entry(); /* execution does not return */
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halt();
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}
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/* TSC cannot be relied upon. Override the TSC value passed in. */
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bootblock_main_with_basetime(timestamp_get());
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}
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void bootblock_soc_early_init(void)
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{
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/*
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* This call (sb_reset_i2c_slaves) was originally early at
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* bootblock_c_entry, but had to be moved here. There was an
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* unexplained delay in the middle of the i2c transaction when
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* we had it in bootblock_c_entry. Moving it to this point
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* (or adding delays) fixes the issue. It seems like the processor
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* just pauses but we don't know why.
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*/
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sb_reset_i2c_slaves();
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bootblock_fch_early_init();
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post_code(0x90);
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}
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void bootblock_soc_init(void)
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{
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if (CONFIG(STONEYRIDGE_UART))
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assert(CONFIG_UART_FOR_CONSOLE >= 0
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&& CONFIG_UART_FOR_CONSOLE <= 1);
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u32 val = cpuid_eax(1);
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printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
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bootblock_fch_init();
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/* Initialize any early i2c buses. */
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i2c_soc_early_init();
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}
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