bccbbe6b69
Hence drop the FALLBACK_ prefix Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6204 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
57 lines
1.5 KiB
Plaintext
57 lines
1.5 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2009 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config NORTHBRIDGE_INTEL_I945GC
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bool
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select HAVE_DEBUG_RAM_SETUP
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config NORTHBRIDGE_INTEL_I945GM
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bool
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select HAVE_DEBUG_RAM_SETUP
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if NORTHBRIDGE_INTEL_I945GC || NORTHBRIDGE_INTEL_I945GM
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config VGA_BIOS_ID
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string
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default "8086,27a2"
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config CHANNEL_XOR_RANDOMIZATION
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bool
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default n
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config OVERRIDE_CLOCK_DISABLE
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bool
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default n
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help
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Usually system firmware turns off system memory clock
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signals to unused SO-DIMM slots to reduce EMI and power
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consumption.
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However, some boards do not like unused clock signals to
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be disabled.
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config MAXIMUM_SUPPORTED_FREQUENCY
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int
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default 0
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help
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If non-zero, this designates the maximum DDR frequency
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the board supports, despite what the chipset should be
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capable of.
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endif
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