bda870242e
Change-Id: Ic99e61632664f86cc12507f2ddffa364fdd79202 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36585 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
110 lines
3.5 KiB
C
110 lines
3.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/cpu.h>
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#include <program_loading.h>
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#include <commonlib/region.h>
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#include <console/console.h>
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#include <cpu/x86/mtrr.h>
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/* For now this is a good lowest common denominator for the total CPU cache.
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TODO: fetch the total amount of cache from CPUID leaf2. */
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#define MAX_CPU_CACHE (256 * KiB)
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/* This makes the 'worst' case assumption that all cachelines covered by
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the MTRR, no matter the caching type, are filled and not overlapping. */
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static uint32_t max_cache_used(void)
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{
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msr_t msr = rdmsr(MTRR_CAP_MSR);
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int i, total_mtrrs = msr.lo & MTRR_CAP_VCNT;
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uint32_t total_cache = 0;
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for (i = 0; i < total_mtrrs; i++) {
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msr_t mtrr = rdmsr(MTRR_PHYS_MASK(i));
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if (!(mtrr.lo & MTRR_PHYS_MASK_VALID))
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continue;
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total_cache += ~(mtrr.lo & 0xfffff000) + 1;
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}
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return total_cache;
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}
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void platform_prog_run(struct prog *prog)
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{
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const uint32_t base = region_device_offset(&prog->rdev);
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const uint32_t size = region_device_sz(&prog->rdev);
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const uint32_t end = base + size;
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const uint32_t cache_used = max_cache_used();
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/* This will accumulate MTRR's as XIP stages are run.
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For now this includes bootblock which sets ups its own
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caching elsewhere, verstage and romstage */
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int mtrr_num = get_free_var_mtrr();
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uint32_t mtrr_base;
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uint32_t mtrr_size = 4 * KiB;
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struct cpuinfo_x86 cpu_info;
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get_fms(&cpu_info, cpuid_eax(1));
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/*
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* An unidentified combination of speculative reads and branch
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* predictions inside WRPROT-cacheable memory can cause invalidation
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* of cachelines and loss of stack on models based on NetBurst
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* microarchitecture. Therefore disable WRPROT region entirely for
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* all family F models.
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*/
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if (cpu_info.x86 == 0xf) {
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printk(BIOS_NOTICE,
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"PROG_RUN: CPU does not support caching ROM\n"
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"The next stage will run slowly!\n");
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return;
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}
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if (mtrr_num == -1) {
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printk(BIOS_NOTICE,
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"PROG_RUN: No MTRR available to cache ROM!\n"
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"The next stage will run slowly!\n");
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return;
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}
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if (cache_used + mtrr_size > MAX_CPU_CACHE) {
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printk(BIOS_NOTICE,
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"PROG_RUN: No more cache available for the next stage\n"
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"The next stage will run slowly!\n");
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return;
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}
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while (1) {
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if (ALIGN_DOWN(base, mtrr_size) + mtrr_size >= end)
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break;
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if (cache_used + mtrr_size * 2 > MAX_CPU_CACHE)
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break;
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mtrr_size *= 2;
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}
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mtrr_base = ALIGN_DOWN(base, mtrr_size);
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if (mtrr_base + mtrr_size < end) {
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printk(BIOS_NOTICE, "PROG_RUN: Limiting XIP cache to %uKiB!\n",
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mtrr_size / KiB);
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/* Check if we can cover a bigger range by aligning up. */
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const uint32_t alt_base = ALIGN_UP(base, mtrr_size);
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const uint32_t lower_coverage = mtrr_base + mtrr_size - base;
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const uint32_t upper_coverage = MIN(alt_base + mtrr_size, end) - alt_base;
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if (upper_coverage > lower_coverage)
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mtrr_base = alt_base;
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}
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printk(BIOS_DEBUG,
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"PROG_RUN: Setting MTRR to cache XIP stage. base: 0x%08x, size: 0x%08x\n",
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mtrr_base, mtrr_size);
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set_var_mtrr(mtrr_num, mtrr_base, mtrr_size, MTRR_TYPE_WRPROT);
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}
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