bdd06de15d
coreboot boots from the little core, and doesn't use the big core for now, but if apll_b is set to the default 24MHz, it will take a long time to enable the big core. This will cause a watchdog crash, so apll_b initialization to 600MHz needs to be done in coreboot. BRANCH=none BUG=chrome-os-partner:54817 TEST=Pick CL:353762 and see big CPU clocks look right TEST=Boot from Gru and see no cpufreq warnings Change-Id: Ie45cd2271555942e4321e9a9e523dc10f63d8107 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: Original-Change-Id: I20b8b591db3171e27740d85edce11f9e8797d849 Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Original-Commit-Id: 16bc916174042620bebe19ae73d241002491aecc Original-Original-Change-Id: Id3487138b383b6643ba7e3ce1eae501a6622da10 Original-Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Original-Reviewed-on: https://chromium-review.googlesource.com/356399 Original-Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15583 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
41 lines
1.1 KiB
C
41 lines
1.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <bootblock_common.h>
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#include <soc/grf.h>
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#include <soc/mmu_operations.h>
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#include <soc/clock.h>
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void bootblock_soc_init(void)
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{
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rkclk_init();
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rkclk_configure_cpu(APLL_600_MHZ, false);
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/* all ddr range non-secure */
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write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xff << 16 | 0);
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/* tzma_rosize = 0, all sram non-secure */
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write32(&rk3399_pmusgrf->soc_con4, 0x3ff << 16 | 0);
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/* emmc master secure */
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write32(&rk3399_pmusgrf->soc_con7, 1 << 23 | 1 << 24 | 0 << 8 | 0 << 7);
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/* glb_slv_secure_bypass */
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write32(&rk3399_pmusgrf->pmu_slv_con0, 1 << 16 | 1);
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rockchip_mmu_init();
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}
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