bddef0dae7
This introduces a Kconfig option to include common Intel SPI code. Change-Id: I970408e5656c0e8812b8609e2cc10d0bc8d8f6f2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
113 lines
3.0 KiB
Plaintext
113 lines
3.0 KiB
Plaintext
##
|
|
## This file is part of the coreboot project.
|
|
##
|
|
## Copyright (C) 2011 Google Inc.
|
|
##
|
|
## This program is free software; you can redistribute it and/or modify
|
|
## it under the terms of the GNU General Public License as published by
|
|
## the Free Software Foundation; version 2 of the License.
|
|
##
|
|
## This program is distributed in the hope that it will be useful,
|
|
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
## GNU General Public License for more details.
|
|
##
|
|
|
|
config SOUTHBRIDGE_INTEL_BD82X6X
|
|
bool
|
|
|
|
config SOUTHBRIDGE_INTEL_C216
|
|
bool
|
|
|
|
if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216
|
|
|
|
config SOUTH_BRIDGE_OPTIONS # dummy
|
|
def_bool y
|
|
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
|
|
select SOUTHBRIDGE_INTEL_COMMON
|
|
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
|
|
select SOUTHBRIDGE_INTEL_COMMON_SPI
|
|
select IOAPIC
|
|
select HAVE_HARD_RESET
|
|
select HAVE_USBDEBUG_OPTIONS
|
|
select HAVE_SMI_HANDLER
|
|
select USE_WATCHDOG_ON_BOOT
|
|
select PCIEXP_ASPM
|
|
select PCIEXP_COMMON_CLOCK
|
|
select COMMON_FADT
|
|
select ACPI_SATA_GENERATOR
|
|
select HAVE_INTEL_FIRMWARE
|
|
select SOUTHBRIDGE_INTEL_COMMON_GPIO
|
|
select RTC
|
|
select HAVE_INTEL_CHIPSET_LOCKDOWN
|
|
|
|
config EHCI_BAR
|
|
hex
|
|
default 0xfef00000
|
|
|
|
config DRAM_RESET_GATE_GPIO
|
|
int
|
|
default 60
|
|
|
|
config BOOTBLOCK_SOUTHBRIDGE_INIT
|
|
string
|
|
default "southbridge/intel/bd82x6x/bootblock.c"
|
|
|
|
config SERIRQ_CONTINUOUS_MODE
|
|
bool
|
|
default n
|
|
help
|
|
If you set this option to y, the serial IRQ machine will be
|
|
operated in continuous mode.
|
|
|
|
config HPET_MIN_TICKS
|
|
hex
|
|
default 0x80
|
|
|
|
config HAVE_IFD_BIN
|
|
def_bool y
|
|
|
|
config BUILD_WITH_FAKE_IFD
|
|
def_bool !HAVE_IFD_BIN
|
|
|
|
endif
|
|
|
|
if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 || SOUTHBRIDGE_INTEL_IBEXPEAK
|
|
|
|
choice
|
|
prompt "Flash locking during chipset lockdown"
|
|
default LOCK_SPI_FLASH_NONE
|
|
|
|
config LOCK_SPI_FLASH_NONE
|
|
bool "Don't lock flash sections"
|
|
|
|
config LOCK_SPI_FLASH_RO
|
|
bool "Write-protect all flash sections"
|
|
help
|
|
Select this if you want to write-protect the whole firmware flash
|
|
chip. The locking will take place during the chipset lockdown, which
|
|
is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set)
|
|
or has to be triggered later (e.g. by the payload or the OS).
|
|
|
|
NOTE: If you trigger the chipset lockdown unconditionally,
|
|
you won't be able to write to the flash chip using the
|
|
internal programmer any more.
|
|
|
|
config LOCK_SPI_FLASH_NO_ACCESS
|
|
bool "Write-protect all flash sections and read-protect non-BIOS sections"
|
|
help
|
|
Select this if you want to protect the firmware flash against all
|
|
further accesses (with the exception of the memory mapped BIOS re-
|
|
gion which is always readable). The locking will take place during
|
|
the chipset lockdown, which is either triggered by coreboot (when
|
|
INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g.
|
|
by the payload or the OS).
|
|
|
|
NOTE: If you trigger the chipset lockdown unconditionally,
|
|
you won't be able to write to the flash chip using the
|
|
internal programmer any more.
|
|
|
|
endchoice
|
|
|
|
endif
|