be291e8abf
This moves FSP1.1 to use postcar stage to tear down CAR. On platforms with USE_GENERIC_FSP_CAR_INC the FSP header is found during the postcar stage so there is no need to push to save it in CAR global variables. On FSP1.1 platforms with an open source CAR implementation (Skylake, even though it still runs the FSP-T), the soc/intel/common/blocks/cpu/car/exit_car.S code tears down CAR. This also uses common functions to set up the MTRR to use after CAR is torn down. Test: build/boot on google/celes (BSW) and google/chell (SKL) Change-Id: I2330993842aae9c1365230f0c6bd8a2449dc73a5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
77 lines
1.9 KiB
Makefile
77 lines
1.9 KiB
Makefile
ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
|
|
|
|
subdirs-y += romstage
|
|
subdirs-y += ../../../cpu/x86/lapic
|
|
subdirs-y += ../../../cpu/x86/mtrr
|
|
subdirs-y += ../../../cpu/x86/smm
|
|
subdirs-y += ../../../cpu/x86/tsc
|
|
subdirs-y += ../../../cpu/intel/microcode
|
|
subdirs-y += ../../../cpu/intel/turbo
|
|
subdirs-y += ../../../cpu/intel/common
|
|
|
|
romstage-y += gpio_support.c
|
|
romstage-y += iosf.c
|
|
romstage-y += lpc_init.c
|
|
romstage-y += memmap.c
|
|
romstage-y += pmutil.c
|
|
romstage-y += smbus.c
|
|
romstage-y += tsc_freq.c
|
|
|
|
postcar-y += memmap.c
|
|
postcar-y += iosf.c
|
|
postcar-y += tsc_freq.c
|
|
|
|
ramstage-y += acpi.c
|
|
ramstage-y += chip.c
|
|
ramstage-y += cpu.c
|
|
ramstage-$(CONFIG_ELOG) += elog.c
|
|
ramstage-y += emmc.c
|
|
ramstage-y += gpio.c
|
|
ramstage-y += gfx.c
|
|
|
|
ramstage-y += gpio_support.c
|
|
ramstage-y += iosf.c
|
|
ramstage-y += lpe.c
|
|
ramstage-y += lpss.c
|
|
ramstage-y += memmap.c
|
|
ramstage-y += northcluster.c
|
|
ramstage-y += pcie.c
|
|
ramstage-y += pmutil.c
|
|
ramstage-y += ramstage.c
|
|
ramstage-y += sata.c
|
|
ramstage-y += scc.c
|
|
ramstage-y += sd.c
|
|
ramstage-y += smm.c
|
|
ramstage-y += southcluster.c
|
|
ramstage-y += spi.c
|
|
ramstage-y += tsc_freq.c
|
|
ramstage-y += xhci.c
|
|
|
|
# Remove as ramstage gets fleshed out
|
|
ramstage-y += placeholders.c
|
|
smm-y += lpc_init.c
|
|
smm-y += pmutil.c
|
|
smm-y += smihandler.c
|
|
smm-y += spi.c
|
|
smm-y += tsc_freq.c
|
|
|
|
verstage-y += pmutil.c
|
|
verstage-y += tsc_freq.c
|
|
|
|
CPPFLAGS_common += -I$(src)/soc/intel/braswell/
|
|
CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
|
|
CPPFLAGS_common += -I$(call strip_quotes,$(CONFIG_FSP_HEADER_PATH))
|
|
|
|
CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR)
|
|
|
|
ifneq ($(CONFIG_VGA_BIOS_FILE),)
|
|
#we will assume that the vbios names will remain as they are now: vgabios.bin and vgabios_c0.bin
|
|
BRASWELL_C0_VBIOS= $(subst .bin,_c0.bin,$(call strip_quotes,$(CONFIG_VGA_BIOS_FILE)))
|
|
|
|
cbfs-files-$(CONFIG_VGA_BIOS) += pci8086,22b1.rom
|
|
pci8086,22b1.rom-file := $(BRASWELL_C0_VBIOS)
|
|
pci8086,22b1.rom-type := optionrom
|
|
endif # ifneq ($(CONFIG_VGA_BIOS_FILE),)
|
|
|
|
endif # ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
|