be61a17351
which uses it. Compiles, but not boot tested lately. Many things missing (eg. SMM support, proper ACPI, ...) Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
50 lines
1.6 KiB
C
50 lines
1.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdint.h>
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#include <console/console.h>
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#include <usbdebug.h>
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#include <device/pci_def.h>
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/* Required for successful build, but currently empty. */
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void set_debug_port(unsigned int port)
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{
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/* Not needed, the southbridges hardcode physical USB port 1. */
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}
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void sch_enable_usbdebug(unsigned int port)
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{
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u32 dbgctl;
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device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
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/* Set the EHCI BAR address. */
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pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
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/* Enable access to the EHCI memory space registers. */
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pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
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/* Force ownership of the Debug Port to the EHCI controller. */
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printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
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dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
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dbgctl |= (1 << 30);
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write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);
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}
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