be9533aba9
The i82801ix_early_init is now called both in the bootblock and romstage. The rationale behind setting this up twice is to ensure bootblock-romstage compatibility in the future if for instance VBOOT is used. This moves the console init to the bootblock. The romstage now runs uncached. Adding a prog_run hooks to set up an MTRR to cache the romstage will be done in a followup patch. The default size of 64KiB is not modified for the bootblock as trying to fit both EHCI and SPI flash debugging needs a more space and 64KiB is the next power of 2 size that fits it. TESTED on Thinkpad X200. Change-Id: I8f59736cb54377973215f35e35d2cbcd1d82c374 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
48 lines
1.0 KiB
Plaintext
48 lines
1.0 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2009 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config NORTHBRIDGE_INTEL_GM45
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bool
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if NORTHBRIDGE_INTEL_GM45
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config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
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def_bool y
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select HAVE_DEBUG_RAM_SETUP
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select VGA
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select INTEL_EDID
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select INTEL_GMA_ACPI
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select INTEL_GMA_SSC_ALTERNATE_REF
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select PARALLEL_MP
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select C_ENVIRONMENT_BOOTBLOCK
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config CBFS_SIZE
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hex
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default 0x100000
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config VGA_BIOS_ID
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string
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default "8086,2a42"
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config MMCONF_BASE_ADDRESS
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hex
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default 0xf0000000
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config SMM_RESERVED_SIZE
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hex
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default 0x100000
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endif
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