bebd766f16
Calling disable_cache_as_ram() with valuables in stack is not a stable solution, as per documentation AMD_DISABLE_STACK should destroy stack in cache. While we still preserve cache contents (there is wbinvd deep inside AMD_DISABLE_STACK macro), we now actually do a stack switch and much more closely meet the specification of CAR teardown sequence in AGESA specifications. We now somewhat incorrectly include files from agesa/ tree, but the whole agesawrapper.c file removal will address the issue of overall directory layout. Change-Id: I2bac098099c1caffea181356c63924f4b5a93b54 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
28 lines
927 B
Makefile
28 lines
927 B
Makefile
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2011 - 2016 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01
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subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
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subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01
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ramstage-$(CONFIG_SPI_FLASH) += spi.c
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cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc
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romstage-y += romstage.c
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romstage-y += ../agesa/heapmanager.c
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ramstage-y += ../agesa/heapmanager.c
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ramstage-y += amd_late_init.c
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